Назад
Company hidden
4 часа назад

DFT Engineer (Semiconductor)

121 900 - 195 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
DFT Engineer (Semiconductor): Developing and debugging ATPG and MBIST test patterns for networking switches used in traditional and AI data centers with an accent on yield enhancement, silicon bring-up, and failure analysis. Focus on scan diagnostics, wafer sort and final test optimization, correlating electrical failures with semiconductor manufacturing data, and building AI-assisted yield analytics and automation.

Location: Onsite at the R&D center in San Jose, California, USA

Annual base salary: USD 121,900–195,000, plus discretionary annual bonus and equity awards.

Company

hirify.global's Core Switching Group develops networking switches for scale-up and scale-out traditional and AI data centers.

What you will do

  • Generate, bring up, convert, and debug ATPG and MBIST DFT patterns for post-silicon testing.
  • Monitor wafer sort and final test yields, binning distributions, and parametric data to drive yield and cost improvements.
  • Perform scan diagnostics, MBIST and repair debugging, root-cause analysis, and electrical fault isolation.
  • Correlate electrical failures with fab metrology, defect density, and process tool data.
  • Partner with Global Operations during NPI and silicon bring-up to debug test programs, validate DFT structures, and establish baseline yield limits.
  • Build automated dashboards, spatial wafer maps, and yield correlation models using data analytics and AI tools.

Requirements

  • Bachelor's degree with 8+ years of related experience, or master's degree with 6+ years of related experience.
  • Deep knowledge of CMOS device physics, semiconductor manufacturing processes, and electrical testing methodologies.
  • Experience with SCAN, MBIST, boundary scan, embedded memories, and PHY/IO testability features.
  • Experience developing scan flows, generating ATPG patterns, and performing verification and coverage analysis.
  • Experience with Mentor/Siemens DFT Tessent for scan, MBIST, BSCAN, and IJTAG pattern generation and debugging.
  • Strong pre- and post-silicon debugging, data analysis, scripting, problem-solving, project management, and organizational skills.

Nice to have

  • Experience using AI tools for rapid script development.

Culture & Benefits

  • Cross-functional collaboration with Product Engineering, Test Engineering, and Global Operations.
  • Medical, dental, and vision plans.
  • 401(k) participation with company matching and an Employee Stock Purchase Program.
  • Company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leaves.
  • Employee Assistance Program, annual bonus eligibility, and equity awards.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →