Staff Digital Design Engineer (ASIC)

Location: Zhubei, Taiwan; remote work is not available

Company

hirify.global is an embedded semiconductor solution provider developing technology for automotive, industrial, infrastructure, and IoT applications.

What you will do

• Design optimized digital blocks that meet functional, cost, low-power, and specification requirements.
• Execute the digital backend flow, including synthesis, UPF, static timing analysis, and logic equivalence checking.
• Coordinate digital handoff with P&R and perform post-layout verification.
• Collaborate with analog and test engineers on analog testability design and debugging.
• Support FPGA prototyping, application/GUI integration, and lab debugging.
• Perform physical silicon device evaluation when required.

Requirements

• 7+ years of experience in ASIC/IC design.
• Deep knowledge of the complete IC design flow, from RTL coding and synthesis through STA, logic equivalence checking, and post-layout checking.
• Fluent Verilog RTL coding and understanding of ASIC design methodology.
• Ability to develop design constraints for synthesis, STA, and P&R handoff.
• Ability to work independently and collaboratively, with strong communication and organizational skills.

Nice to have

• Experience in DFT or physical design.
• Experience with FPGA prototypes, lab equipment, and laboratory debugging.

Culture & Benefits

• Regular permanent employment with a full-time schedule.
• Competitive benefits package alongside salary.
• Global environment with more than 21,000 engineers and problem solvers across over 30 countries.
• Culture grounded in transparency, agility, global collaboration, innovation, and entrepreneurship.