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18 часов назад

Senior Emulation Engineer

138 000 - 206 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Emulation Engineer (Hardware Emulation/FPGA): Building and maintaining large-scale hardware emulation and FPGA prototyping platforms for memory-centric computing SoCs with an accent on pre-silicon validation, multi-FPGA partitioning, and software bring-up. Focus on developing SCE-MI co-emulation environments, modeling memory and high-speed interfaces, automating flows, and debugging AI/ML workloads across hardware and software teams.

Location: Daily onsite presence in San Jose, California, United States

Base pay: $138,000–$206,000 USD per year, plus incentive opportunities.

Company

hirify.global develops technology solutions and scalable computing platforms for AI/ML workloads, memory-centric computing, IoT devices, electric vehicles, and data centers.

What you will do

  • Build, bring up, and maintain large-scale hardware emulation and FPGA prototyping platforms for memory-centric computing SoCs.
  • Partition and map multi-million-gate ASIC/SoC designs onto emulation systems and multi-FPGA prototypes, optimizing capacity, performance, and debug visibility.
  • Develop transactors, speed bridges, and SCE-MI co-emulation environments connecting designs under test with host software and virtual or physical interfaces.
  • Model memory subsystems, clock and reset schemes, and high-speed interfaces such as PCIe, DDR/HBM, AXI/CHI, and Ethernet.
  • Enable firmware, driver, and software bring-up, then run AI/ML workloads and pre-silicon performance benchmarks.
  • Automate compilation, partitioning, and build flows while debugging hardware and software issues with design, verification, and software teams.

Requirements

  • Bachelor’s degree with 5+ years, Master’s degree with 3+ years, or PhD with 0+ years of industry experience.
  • 5+ years of experience with both FPGA prototyping and large-scale hardware emulation of complex ASIC/SoC designs.
  • Hands-on experience with Cadence Palladium, Synopsys ZeBu, Siemens Veloce, Synopsys HAPS, or Cadence Protium.
  • Experience with multi-FPGA partitioning, timing closure, transactors, SCE-MI co-emulation, and speed bridges.
  • Proficiency in Verilog/SystemVerilog, memory modeling, clocking, reset, SoC bring-up, and pre-silicon verification and validation.
  • Proficiency in Tcl, Python, or Perl for flow automation, plus experience running AI/ML workloads or system-level software pre-silicon.

Nice to have

  • Familiarity with agentic AI tools and frameworks for emulation and prototyping automation.

Culture & Benefits

  • Inclusive, collaborative environment supporting diverse perspectives and working styles.
  • Medical, dental, vision, 401(k), paid time off of 4+ weeks annually, holidays, and sick leave.
  • Family support benefits, including fertility and adoption assistance, medical travel support, and virtual veterinary care.
  • Emotional wellness resources, including confidential therapy sessions and on-demand wellness apps.
  • Onsite café and gym, virtual fitness classes, charitable giving match, and a flexible work environment within the onsite role requirements.

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