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5 дней назад

Design Automation / Standard Cell Characterization Engineer (NAND/ASIC)

121 280 - 194 100$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Design Automation / Standard Cell Characterization Engineer (NAND/ASIC): Building and delivering standard cell library characterization, automation, QA infrastructure, and digital frontend enablement for advanced NAND/ASIC programs with an accent on production-quality library collateral, synthesis, STA, and physical design integration. Focus on developing scalable Python, Perl, Tcl, and Bash automation, validating timing and power models across process and voltage corners, and supporting RTL-to-GDS flows and tapeouts.

Location: San Jose, California, United States; onsite full-time

Salary: USD 121,280–194,100 per year, plus eligibility for RSU, RCU, and cash bonus programs.

Company

hirify.global is a global memory technology company developing NAND products and optimized data storage solutions.

What you will do

  • Develop end-to-end standard cell library characterization and release flows, including nominal and low-voltage characterization.
  • Deliver library collateral such as .lib, LEF, GDS, CDL, Verilog, and NDM files.
  • Build scalable design automation, QA, validation, comparison, and reporting frameworks using Python, Perl, Tcl, and Bash.
  • Enable synthesis and static timing analysis flows with Design Compiler, Fusion Compiler, and PrimeTime.
  • Support place-and-route, full-chip integration, ECO automation, timing closure, and netlist-to-GDS flows.
  • Partner with RTL, frontend, backend, PDK, and CAD teams during production releases and tapeouts.

Requirements

  • MS in Electrical Engineering or a related field.
  • 5+ years of experience in standard cell library characterization, validation, and production collateral delivery.
  • 5+ years of experience in design automation and EDA flow development.
  • Hands-on experience with digital frontend flows, synthesis, and STA.
  • Strong expertise with Synopsys Siliconsmart, Fusion Compiler, Design Compiler, and PrimeTime, plus experience with Cadence Virtuoso and Conformal.
  • Strong scripting proficiency in Python, Perl, Tcl, and Bash.

Nice to have

  • Library enablement for RTL-to-GDSII flows and timing model or constraint validation.
  • Experience with AOCV, variation-aware timing, MCMM methodology, and synthesis QoR analysis.
  • Experience building large-scale QA and validation frameworks.
  • Exposure to NAND/ASIC tapeout environments and end-to-end design flows.

Culture & Benefits

  • Medical, dental, vision, supplemental life, and AD&D insurance.
  • Short- and long-term disability coverage and healthcare and dependent care FSAs.
  • Company match on eligible 401(k) plan contributions.
  • Work in a diverse, inclusive, collaborative, and results-driven environment.

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