Principal Design Verification Engineer

Location: Santa Clara, California, United States; onsite

Salary: $158,600–$317,800 per year, plus bonus and RSUs.

Company

Software development company building scalable, secure, and user-friendly solutions that automate and optimize business operations.

What you will do

• Lead design verification efforts for complex SoC projects.
• Develop and maintain verification environments with SystemVerilog and UVM.
• Create verification plans and tests, and drive coverage closure.
• Debug verification failures and collaborate closely with design teams.
• Build automation tools using Python or Perl and support boot code verification and multi-core SoC validation.
• Mentor and lead verification engineers.

Requirements

• 10+ years of design verification experience, or an MS/PhD with 5+ years of experience.
• Strong SystemVerilog and UVM experience.
• SoC/ASIC verification experience with successful tape-outs.
• Expertise in constrained-random and coverage-driven verification.
• Experience with EDA verification tools, Linux, C++, object-oriented programming, and Python or Perl scripting.
• BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.

Nice to have

• ARM Assembly experience.

Culture & Benefits

• Onsite work in Santa Clara.
• Bonus and RSU compensation.
• Relocation assistance available.
• Visa sponsorship available.
• Inclusive work environment and equal employment opportunity commitment.