Manager, ATE Test Engineering (AI Infrastructure)

Location: San Jose, California, United States

Salary: $195,000–$250,000 per year, depending on experience, level, and business need. Eligibility for discretionary bonuses, incentives, and benefits may apply.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and its COSMOS software suite, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

• Build, mentor, and lead a high-performing ATE Test Engineering team developing connectivity products for AI infrastructure.
• Define end-to-end ATE test strategies covering design engagement, silicon bring-up, wafer sort, final test, production release, and high-volume manufacturing.
• Set and improve coverage, quality, yield, cost, and test-time objectives across the product lifecycle.
• Guide tester platform selection and development of load boards, interface hardware, ATE programs, patterns, and test solutions.
• Direct characterization, production testing, debug, and bench-to-ATE correlation for high-speed SerDes and mixed-signal interfaces.
• Coordinate with design, DFT, product engineering, operations, manufacturing, and external manufacturing partners on readiness and release decisions.

Requirements

• Bachelor’s degree in electrical engineering or a related technical field.
• 8+ years of experience developing and supporting ATE test solutions for complex high-speed or SoC products.
• 3+ years of managerial experience building and leading a Test Engineering team.
• Working knowledge of PCIe, Ethernet, DDR, NVMe, or USB protocols and physical-layer behavior.
• Experience with ATE program development, silicon bring-up, bench-to-ATE correlation, production debug, and test-time optimization.
• Ability to communicate clearly, manage competing priorities, and collaborate across technical and manufacturing organizations.

Nice to have

• Master’s or PhD in Electrical Engineering or a related field.
• Experience leading wafer-sort and final-test hardware development, including high-speed load-board design.
• Knowledge of SCAN, MBIST, SerDes, functional testing, I2C, I3C, SPI, MDIO, and JTAG.
• Experience testing SerDes operating at 16 Gbps or higher, including external loopback at wafer sort.
• Proficiency in C, C++, or Python for ATE programming, data processing, and automation; familiarity with databases and RF testing on ATE platforms.

Culture & Benefits

• Fast-paced, high-growth environment focused on technical depth, rigorous execution, and continuous improvement.
• Cross-functional work with design, DFT, product engineering, operations, manufacturing, and ecosystem partners.
• Discretionary bonuses, incentives, and benefits may be available.
• Commitment to diverse ideas, backgrounds, and experiences, with encouragement for candidates from underrepresented groups, veterans, parents, and people with disabilities.