Staff Design Verification Engineer (RISC-V)

Location: Austin, Texas, United States. The role requires satisfactory proof of the right to work in the United States of America and authorization to access export-controlled technology or the necessary export license.

Company

hirify.global develops high-performance RISC-V compute platforms and processor technologies for applications including artificial intelligence, automotive, data centers, mobile, and consumer products.

What you will do

• Own verification planning and execution for a scalable cache-coherent interconnect subsystem from block level through subsystem integration.
• Develop reusable SystemVerilog and UVM environments, checkers, scoreboards, stimulus, assertions, and coverage models.
• Verify coherent traffic, ordering, backpressure, flow control, error handling, QoS, arbitration, virtual networks, and transport-level correctness.
• Validate protocol adaptation and bridge paths involving conversion, buffering, deinterleaving, and related data movement.
• Define directed and constrained-random scenarios that expose coherency, concurrency, ordering, credit, and integration corner cases.
• Partner with architecture, design, formal, and software teams to debug failures, close coverage, and improve verification methodology and infrastructure.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of ASIC or SoC design verification experience; the description also references 5–8 years of relevant IP or component verification experience.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory systems, computer architecture, and complex protocol behavior.
• Experience building reusable testbench components, assertions, coverage models, debug infrastructure, and object-oriented software.
• Ability to root-cause issues across specifications, RTL, and testbench layers while collaborating across architecture, design, and verification teams.

Nice to have

• Experience with coherent interconnects, NoCs, memory fabrics, or large subsystem integration.
• Experience with AXI, CHI, CXL, UCIe, or similar high-performance interface protocols.
• Experience with formal verification, performance-oriented verification, emulation, FPGA-assisted debug, or protocol-conversion subsystems.
• Familiarity with Python or other scripting languages for verification infrastructure and automation.
• Experience mentoring engineers and improving team-wide verification quality.

Culture & Benefits

• Collaboration with architecture, design, formal, and software teams on high-performance RISC-V processor technologies.
• Work within a high-performance Out-of-Order Core team covering frontend, mid-core, load-store, integer and floating-point execution, and RVV vector units.
• Competitive benefits may include healthcare, retirement plans, and paid time off.
• Additional compensation may include variable or incentive compensation and equity.
• Employment is contingent on successful background and reference checks, employment eligibility verification, and export-control authorization.