Staff Verification Engineer (UVM)

Location: Raanana, Israel; on-site role with remote work available

Company

Global embedded semiconductor solution provider developing power-efficient technologies for automotive, industrial, infrastructure, and IoT applications.

What you will do

• Develop and maintain UVM-based verification environments for complex IP and SoC designs.
• Write testbenches, test cases, coverage models, and verification plans.
• Define and execute verification scenarios based on circuit-level and system-level specifications.
• Run regressions, monitor coverage metrics, debug RTL issues, and perform root-cause analysis of failures.
• Collaborate with design, architecture, and firmware teams on verification and design reviews.
• Improve verification methodologies and automation, and potentially mentor junior engineers.

Requirements

• Strong hardware verification expertise, including UVM and constrained-random verification.
• Experience with formal verification techniques and tools.
• Understanding of computer architecture, memory hierarchies, bus protocols, and high-performance compute subsystems.
• Hands-on RTL design experience with Verilog/SystemVerilog, synthesis considerations, and design-for-verification practices.
• Proficiency with simulators, waveform viewers, coverage tools, regression management, and Python, Perl, or Tcl scripting.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, plus cross-functional communication skills.

Nice to have

• Experience in semiconductor product development for automotive, industrial, or embedded systems.

Culture & Benefits

• Work with colleagues across a global organization spanning more than 30 countries.
• Collaborative, transparent, agile, innovative, and entrepreneurial working culture.
• Projects focused on sustainable, power-efficient semiconductor solutions.
• Competitive benefits package alongside salary; details are provided during the hiring process.