ASIC Verification Engineer

Location: Onsite, primarily from an hirify.global office

Company

Hewlett Packard Enterprise is a global edge-to-cloud technology company developing solutions that connect, protect, analyze, and manage data and applications.

What you will do

• Develop and enhance ASIC verification environments using SystemVerilog and UVM.
• Architect block-level, subsystem, and full-chip verification environments.
• Define, design, and execute verification suites and test cases using VCS, NC, and other front-end simulators.
• Verify large ASIC blocks and drive tape-out readiness through code coverage, functional coverage, and gate-level simulation analysis.
• Collaborate with logic designers to debug and resolve design issues, and support software teams during bring-up and validation.
• Develop Perl, Tcl, Python, and/or Shell scripts to automate verification infrastructure and methodologies.

Requirements

• Bachelor's or Master's degree in Electrical Engineering.
• 5+ years of experience in ASIC verification.
• Strong experience with SystemVerilog and constrained-random verification techniques.
• Hands-on experience with OVM, VMM, or UVM methodologies.
• Proficiency in Perl, Tcl, Python, or Shell scripting, with Perl and Tcl preferred.
• Strong problem-solving, debugging, analytical, and collaboration skills.

Nice to have

• Experience verifying networking protocols such as Ethernet.

Culture & Benefits

• Comprehensive health, financial, and emotional wellbeing benefits.
• Personal and professional development programs supporting career growth and movement across divisions.
• Inclusive work environment that values varied backgrounds and individual uniqueness.
• Flexible support for managing work and personal needs.