CPU Verification Fellow (RISC-V)

Location: Hybrid, based out of Santa Clara, California, or Austin, Texas, United States

Compensation: $100,000–$500,000 annually, including base and variable compensation targets

Company

Tenstorrent develops AI computing platforms that combine software, compilers, networking, platforms, and high-performance RISC-V semiconductor technology.

What you will do

• Lead verification strategy and execution for next-generation high-performance RISC-V CPUs and CPU subsystems.
• Plan verification for out-of-order, speculative, superscalar microarchitectures from early design through tapeout and post-silicon validation.
• Build and scale test plans, coverage models, checkers, assertions, scoreboards, and constrained-random verification environments.
• Verify frontend, branch prediction, rename, scheduling, execution, load-store, memory ordering, cache hierarchy, retirement, exceptions, interrupts, debug, and coherency interactions.
• Drive verification across simulation, formal verification, emulation, FPGA prototyping, and silicon bring-up.
• Collaborate with architecture, RTL, performance modeling, SoC, firmware, compiler, and validation teams while mentoring senior engineers.

Requirements

• Deep experience verifying high-performance superscalar CPUs, ideally including out-of-order and speculative processors.
• Strong knowledge of RISC-V architecture, including ISA compliance, privileged architecture, virtual memory, atomics, vector extensions, and memory model behavior.
• High proficiency in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, and advanced debugging.
• Hands-on experience with CPU reference models, instruction generators, ISS-based checking, or differential testing.
• Practical expertise with formal verification and large-scale CPU verification environments.
• Eligibility to access U.S. export-controlled technology is required; employment may depend on citizenship, permanent residency, or obtaining the necessary license approval.

Culture & Benefits

• Collaborative environment focused on curiosity and solving difficult technical problems.
• Exposure to the development of RISC-V processors from early design through tapeout and post-silicon validation.
• Opportunity to work across architecture, design, firmware, compiler, and validation disciplines.
• Competitive compensation package and benefits.
• Equal opportunity employment.