Senior Digital Verification Engineer - Contract

Location: San Francisco Bay Area, Pittsburgh, PA, or Austin, TX

Hourly rate: $80–$130 per hour on a 1099 contract basis

Company

Product company developing energy-efficient computing hardware and software, including a proprietary Fabric architecture and the Electron E1 processor for AI, autonomous machines, intelligent infrastructure, wearables, and space systems.

What you will do

• Own verification of assigned SoC blocks and subsystems from specification review through coverage sign-off.
• Create verification plans from design and architecture specifications and review them with design and architecture leads.
• Architect, build, and extend UVM/SystemVerilog testbenches, including agents, scoreboards, reference models, sequences, and constrained-random tests.
• Develop SystemVerilog assertions and functional coverage models and drive functional and code coverage to closure.
• Debug complex simulation failures, identify root causes, and collaborate with RTL designers on fixes.
• Report verification status, risks, and coverage gaps and document the environment for handoff to the full-time team.

Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of ASIC/SoC design verification experience, including multiple projects taken from testbench development through tapeout.
• Expertise in UVM and SystemVerilog verification, including classes, constraints, interfaces, functional coverage, and SVA.
• Experience driving functional and code coverage to sign-off on multi-million-gate designs.
• Ability to debug complex simulation failures independently using VCS/Verdi, Xcelium, or Questa, with Python for regression automation, log analysis, and coverage processing.
• Ability to ramp quickly, work independently, and communicate verification status, risks, and tradeoffs clearly.

Nice to have

• C/C++ reference modeling, SoC-level testing, or DPI integration.
• Formal verification experience with JasperGold or similar tools.
• Agentic AI flows for design verification, including automated regression triage or failure debugging.
• Experience with computer architecture, dataflow or spatial architectures, ML accelerators, or UPF-based power-aware verification.

Culture & Benefits

• 1099 contractor engagement with a competitive hourly rate and flexibility based on experience, seniority, and location.
• Opportunity to take ownership of complex verification work and contribute to next-generation computing architecture.
• Equity, 401(k) match, company-paid benefits, and paid parental leave are offered as part of the broader company benefits package.
• Opportunities to grow technical skills and career as the organization scales.