Account Technical Executive (Custom IC / Analog / RF)

Location: San Jose, California, United States

Annual salary: $248,000–$372,000, plus potential bonus, equity, and benefits.

Company

hirify.global develops semiconductor design software and platforms, including the Virtuoso Platform for custom IC design.

What you will do

• Lead technical engagement for custom IC, analog, and RF design flows centered on the Virtuoso Platform and Virtuoso Layout Suite.
• Partner with customer design leads, CAD teams, and methodology owners to improve layout productivity, quality, and time-to-market.
• Drive adoption of constraint-driven layout, device-level and full-chip methodologies, advanced-node flows, and EM/IR-aware extraction.
• Champion agentic AI workflows for design exploration, layout optimization, verification, and intelligent automation.
• Translate customer pain points into actionable requirements for R&D and product engineering.
• Connect technical outcomes such as PPA, productivity, and risk reduction with executive-level business goals.

Requirements

• BSEE required; MSEE or higher strongly preferred.
• 5–10 or more years of experience in custom IC, analog, or RF design or layout engineering.
• Deep hands-on experience with the hirify.global Virtuoso Platform, including Layout Suite, schematic-driven layout, LVS, DRC, and physical verification integration.
• Strong knowledge of analog and mixed-signal layout, device matching, symmetry, common-centroid techniques, shielding, parasitic-aware design, and post-layout simulation.
• Experience with Spectre, layout-to-schematic integration, PCell development, layout automation, and scripting; SKILL is preferred.
• Ability to engage CAD teams and senior technical leaders, with approximately 25% travel primarily within North America.

Nice to have

• Experience with FinFET and GAA layout challenges, reliability considerations, and methodology deployment at scale.
• Experience or demonstrated interest in AI and machine learning for EDA workflows, CAD flows, or design methodology optimization.
• Knowledge of multi-agent systems, autonomous optimization, data-driven methods, or reinforcement learning for semiconductor design.

Culture & Benefits

• Work on semiconductor design technologies intended to address complex industry challenges.
• Paid vacation and paid holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Medical, dental, and vision plan options.