Memory Senior Layout Engineer

Location: Da Nang, Hai Chau, Da Nang, Vietnam

Company

Mixel Vietnam develops high-performance, silicon-proven analog mixed-signal semiconductor IPs for mobile, display, camera, automotive, VR, AR, and AI applications as part of hirify.global Group.

What you will do

• Own the layout design and physical verification of critical memory IP blocks, including floorplanning, placement, routing, and signoff.
• Develop custom layouts from schematics, including leaf-cell layouts and compiler-porting re-floorplans optimized for area and parasitic performance.
• Optimize power distribution, routing, and floorplans; perform EMIR analysis and resolve electromigration and IR-drop issues.
• Execute DRC, LVS, ERC/VERC, antenna, ResCheck/CapCheck, and DFM flows, resolving complex violations and implementing ECOs through clean re-verification.
• Develop automation scripts with Perl, Python, TCL, Shell, or SKILL and improve layout methodologies, checklists, and release processes.
• Collaborate with design, modeling, DFT, physical design, CAD, and process teams; mentor junior engineers and support fabricated-silicon validation and debugging.

Requirements

• BS or MS degree in electronics engineering, telecommunications, microelectronics, computer engineering, physics, or a related field.
• At least 4 years of hands-on custom layout design experience for IC or IP development.
• Proficiency with Cadence Virtuoso or an equivalent layout capture tool.
• Proficiency with Calibre, ICV, StarRC, or equivalent layout verification and extraction tools.
• Experience with parasitic extraction, post-layout impact analysis, EMIR, and IR-drop analysis; familiarity with advanced 5nm and 3nm process nodes.
• Fluent written and verbal English, strong communication, analytical, problem-solving, and attention-to-detail skills.

Nice to have

• Direct memory IP layout experience with SRAM, DPRAM, ROM, register files, or TCAM.
• Experience with memory compilers, porting, view-generation flows, and pitch-matched leaf-cell design.
• Familiarity with LEF, GDS, and CDL views and advanced FinFET process nodes.
• Knowledge of ISO 26262 functional-safety and ISO 9001 quality processes.

Culture & Benefits

• Technical environment focused on engineering excellence and meaningful individual contributions.
• Minimal management layers with open communication, empathy, mutual trust, and respect.
• Emphasis on employee well-being and long-term professional development.
• Full-time employment within Mixel Vietnam and the broader hirify.global Group.