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Principal Advanced Packaging Design Engineer

168 400 - 249 310$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal Advanced Packaging Design Engineer (Advanced Packaging): Leading small project teams to design and develop high-performance semiconductor packages for HPC, AI, and networking solutions with an accent on substrate design, signal integrity, power integrity, and manufacturability. Focus on developing 2.5D and 3D package architectures, optimizing HBM and high-speed interconnect designs, and coordinating cross-functional stakeholders and package suppliers.

Location: Burlington, VT, United States

Salary: $168,400–$249,310 per year

Company

hirify.global develops semiconductor solutions for enterprise, cloud and AI, carrier, networking, and high-performance computing infrastructure.

What you will do

  • Lead small project teams of design and simulation engineers delivering advanced packaging solutions.
  • Develop package architectures for high-performance computing, AI, and networking products.
  • Evaluate package technologies and work with suppliers to ensure manufacturability, reliability, performance, and cost compliance.
  • Design and optimize substrates, boards, breakout structures, placement and routing, signal shielding, reference planes, power distribution, and pinouts.
  • Collaborate with chip design, electrical simulation, internal stakeholders, external customers, and cross-functional teams.
  • Contribute to tool, process, flow, and library development and interpret signal and power integrity simulations.

Requirements

  • Bachelor’s degree in electrical engineering or a related field with 15+ years of related experience, master’s degree with 12+ years, or PhD with 8+ years.
  • Extensive experience in substrate and/or board design for advanced package technologies.
  • Proven ability to lead complex package architecture development projects involving internal and external stakeholders.
  • Mastery of Cadence 3DIC, ISP, APD, and SiP tools and workflows.
  • Experience with HBM, DDR, SerDes, D2D, D2H, ADC, DAC, PCIe, Ethernet, and related high-speed interfaces.
  • Ability to work with stakeholders across multiple time zones and communicate technical decisions clearly.

Nice to have

  • Experience with Cadence Sigrity, Clarity, Innovus, Virtuoso, Ansys, AutoCAD, and SolidWorks.
  • Familiarity with signal and power integrity simulations.
  • Experience with advanced 2.5D/3D packaging technologies such as CoWoS, EMIB, CPO, and CPC.

Culture & Benefits

  • Employee stock purchase plan with a two-year lookback.
  • Family support programs for work-life balance.
  • Mental and physical health resources.
  • Recognition and service awards.
  • Employment benefits supporting employees from onboarding through retirement.

Hiring process

  • Interviews evaluate individual experience, thought process, and communication skills.
  • AI tools, transcription apps, answer generators, and automated note-taking bots are not permitted during interviews.
  • Access to export-controlled technology may require an export license review before employment.

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