Sr. Digital Verification Engineer (SystemVerilog)

Location: Taipei, Taiwan

Company

hirify.global develops integrated power semiconductors and power delivery architectures for portable and non-portable markets.

What you will do

• Develop verification plans from design requirements and product datasheets for digital and mixed-signal ICs.
• Collaborate with digital and analog designers on system-level and behavioral models.
• Create verification environments using UVM and SystemVerilog.
• Write digital and mixed-signal test cases, assertions, and checkers.
• Analyze test results, code coverage, and functional coverage, including gate-level verification.
• Develop verification IP, standard tests, environments, and automation scripts using industry-standard ASIC tools.

Requirements

• MS in Electrical Engineering and 5–8 years of experience verifying digital ASIC designs.
• Strong knowledge of ASIC development processes and digital design techniques.
• Strong knowledge of SystemVerilog, UVM, behavioral coding, and RTL coding.
• Experience with digital simulators, coverage analysis tools, and formal verification tools.
• Ability to execute tasks according to design specifications and meet project milestones.
• Strong written and verbal communication, teamwork, and collaboration skills.

Nice to have

• Embedded design or firmware development experience.
• Knowledge of power management applications.
• Experience with I2C, I3C, SPI, USB, or PMBUS.
• Experience with TCL, Python, or C/C++ for scripting and automation.

Culture & Benefits

• Work in a company focused on creativity, sustainability, and semiconductor innovation.
• Collaborate across digital and analog design disciplines.
• Equal employment opportunity and a commitment to diversity.