4 дня назад
Digital Verification Engineer (FPGA/ASIC)
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Digital Verification Engineer (FPGA/ASIC): Building and maintaining verification environments and test suites for digital subsystems across FPGA and ASIC targets with an accent on constrained-random testing, coverage closure, assertions, and simulation debug. Focus on developing reusable testbenches, automating deterministic regressions, debugging waveforms, and validating hardware/software behavior during system bring-up.
Location: Santa Clara, California, United States; hybrid. Travel: 0–10%.
Company
develops switching platforms involving FPGA, ASIC, digital logic, and hardware/software integration.
What you will do
- Design, build, and maintain block-level through full-chip verification environments for FPGA and ASIC targets.
- Develop reusable drivers, monitors, scoreboards, checkers, and behavioral reference models.
- Author directed and constrained-random tests for functional modes, corner cases, error injection, resets, and clock-domain behavior.
- Define functional and code-coverage goals, drive coverage closure, and add SVA assertions for protocol and interface violations.
- Run and debug ModelSim/QuestaSim and NC-Verilog simulations, maintain automated regressions, and produce reproducible failure reports.
- Support FPGA and board bring-up, HW/SW co-validation, register-map and boot-sequence checks, and verification milestone sign-off.
Requirements
- 3–7 years of digital verification experience on FPGA or ASIC designs.
- Proficiency in Verilog; strong SystemVerilog experience is preferred.
- Hands-on experience with ModelSim/QuestaSim and/or NC-Verilog.
- Knowledge of testbench construction, constrained-random stimulus, functional and code coverage, and assertions.
- BS or MS in Electrical Engineering, Computer Engineering, or a related field.
Nice to have
- Knowledge of RTL design, pipelines, clock-domain crossing, bus/interconnect protocols, or digital architecture.
- Experience with UVM or an equivalent structured verification methodology.
- Experience collaborating with firmware/software teams during system bring-up and HW/SW co-validation.
- Familiarity with networking or switching datapaths and high-speed interfaces.
Culture & Benefits
- Close collaboration with RTL designers and firmware engineers.
- Hybrid work arrangement in Santa Clara, California.
- Minimal travel, limited to 0–10%.
- Focus on deterministic regressions, defensible coverage, and reliable hardware bring-up.
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