4 дня назад
DV - Staff (+) Verification Engineer - AMS Modeling
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
DV - Staff (+) Verification Engineer - AMS Modeling (SystemVerilog/UVM): Developing and verifying AMS SystemVerilog RNM models for SerDes PHYs with an accent on mixed-signal verification, analog block understanding, and model fidelity. Focus on writing and debugging UVM-compliant test cases, validating models against schematics, and collaborating with analog and design teams to ensure design quality.
Location: Bay Area, Vancouver, or Toronto; onsite Monday–Friday
Company
is an early-stage chiplet startup developing technologies for chiplet-based systems with a focus on power, area, manufacturability, and design flexibility.
What you will do
- Develop and execute AMS RNM models for SerDes PHYs.
- Verify that model quality accurately reflects circuit schematics.
- Write and debug SystemVerilog and UVM-compliant test cases.
- Own verification of AMS SystemVerilog models.
- Collaborate with analog and design teams to ensure design quality.
Requirements
- 5+ years of relevant experience.
- Bachelor’s degree in electrical engineering or a related field.
- Deep analog design expertise and the ability to understand analog blocks.
- Knowledge of SystemVerilog, verification environments, and assertion coding.
- Experience verifying mixed-signal IP.
- Availability for onsite work Monday–Friday in the Bay Area, Vancouver, or Toronto.
Nice to have
- Formal verification experience with JasperGold or VC Formal.
- Python, Perl, or Tcl scripting experience for design verification.
Culture & Benefits
- Fast-paced early-stage startup environment.
- Hands-on technical work with advanced chiplet and PHY technologies.
- Fun work environment and excellent benefits.
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