Design Verification Lead (ASIC/SoC)

Location: San Jose, United States

Company

hirify.global is a well-funded startup developing photonics infrastructure for AI supercomputing, including optical interconnects and scalable photonic engines.

What you will do

• Define the end-to-end design verification strategy, including verification plans, functional and code coverage, UVM architecture, and signoff criteria from block to full chip.
• Build regression and CI infrastructure with nightly runs before the first RTL handoff.
• Verify in-house engines against algorithmic golden models with programmable error injection and error-pattern coverage.
• Own emulation and FPGA-prototyping methodology, UCIe VIP and compliance scenarios, link training, loopback, lane repair, and performance verification.
• Develop UVM register verification, firmware co-simulation, MCU boot-flow verification, mixed-signal co-simulation, gate-level simulation, and UPF signoff verification.
• Lead and grow the verification team across FEC, UCIe, MCU, datapath, and full-chip areas.

Requirements

• 10+ years of ASIC/SoC verification experience, including leading verification of at least one complex SoC from planning through tapeout.
• Experience with large digital SoCs and subsystems, interconnect fabrics, and full-chip closure.
• Deep expertise in UVM, SystemVerilog, coverage-driven verification, and constrained-random methodologies.
• Hands-on experience with emulation platforms such as Palladium or Veloce and/or FPGA prototyping platforms such as HAPS or Protium.
• Experience with mixed-signal verification using Verilog-AMS or SystemVerilog real models.
• Experience operating regression and CI at scale, including grid management, triage automation, and rigorous coverage closure.

Nice to have

• High-speed SerDes, PAM4, FEC, or Reed-Solomon verification experience.
• UCIe, PCIe/CXL, Ethernet, UALink, or comparable die-to-die and link-layer VIP compliance experience.
• Experience with NIC cards, Ethernet or InfiniBand switches, cache coherency, low-power/UPF, gate-level simulation, performance verification, formal verification, or portable stimulus.

Culture & Benefits

• Comprehensive health, dental, and vision benefits.
• Professional development opportunities and certification support.
• Access to advanced technology and cloud platforms.
• Collaborative work with cross-functional engineering teams.