Principal FEOL/MOL Integration Engineer (Semiconductor)

Location: Albany, TX, United States; onsite office and cleanroom/fab work required

Salary: $148,319.86–$209,424.67 per year

Company

hirify.global engineers, manufactures, sells, and services wafer-processing and semiconductor production equipment, as well as flat-panel display and thin-film photovoltaic equipment.

What you will do

• Act as the principal technical authority for FEOL/MOL process integration while mentoring engineers as a senior individual contributor.
• Define and build process integration routes across lithography, etch, films, wet processes, and CMP, including flow definition, mask planning, and split strategy.
• Establish electrical test capability, covering test structure and PCM design, test-chip planning, probe-card and test-program coordination, and wafer-level parametric extraction.
• Lead cross-business-unit projects across TEL business units, factories, and onsite partners.
• Plan and execute process splits, DOEs, metrology, wafer runs, statistical analysis, and data-driven evaluation.
• Resolve integration and process issues while maintaining rigorous quality, documentation, and data-integrity standards.

Requirements

• FEOL/MOL semiconductor process integration experience, with a record of building processing routes from flow definition through wafer execution.
• At least 8 years of related semiconductor engineering experience with a master's degree, 5 years with a PhD, or 10 years with a bachelor's degree.
• Experience leading cross-functional or cross-business-unit technical projects, including planning and scheduling.
• Hands-on experience with inline CDSEM, cross-sectional SEM, experiment design, and process or tool optimization.
• U.S. work authorization is required.
• Regular cleanroom/fab work is required, including extended use of cleanroom attire and lifting or carrying FOUPs.

Nice to have

• Electrical or parametric test experience with structures such as MOSCAP, TLM, Kelvin, Van der Pauw, and BEOL daisy chains.
• Lot management using SIVIEW MM/SM.
• EUV lithography or 193i immersion experience.
• JMP or equivalent statistical software, Excel, and measurement or analysis tools such as Quartz PCI.
• Prior experience as a principal or senior individual contributor or driving multi-stakeholder technical programs.

Culture & Benefits

• Full-time employment with a comprehensive benefits package.
• Eligibility for bonus plans and long-term incentives may apply to certain roles.
• Work takes place in a highly regulated environment with strict cleanliness and safety protocols.
• The role combines office, laboratory, and cleanroom work, typically involving 4–6 hours per day at a computer.