Назад
Company hidden
обновлено 10 часов назад

Digital IC Implementation Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Digital IC Implementation Engineer (ASIC): Developing next-generation Raspberry Pi silicon from RTL through GDS with an accent on physical design, timing constraints, UPF, synthesis, place and route, and silicon sign-off. Focus on closing performance, power, and area goals, completing tapeout verification, and improving physical design quality through scripting and RTL input.

Location: Cambridge, England, United Kingdom; full-time office attendance required.

Company

hirify.global develops its own silicon, including microcontrollers and southbridge chips for hirify.global products.

What you will do

  • Contribute to the complete physical design flow from RTL to GDS.
  • Work with the design team to understand requirements and close performance, power, and area goals.
  • Develop timing constraints and UPF, and contribute to synthesis, design discovery, place and route, CTS, STA, formal verification, ECO methodology, and physical verification.
  • Support chip-level floorplanning, hierarchical implementation methodologies, and power grid design.
  • Contribute to tapeout sign-off, ATE test, qualification, and production readiness.
  • Share implementation knowledge and mentor other team members.

Requirements

  • Multiple tapeouts on advanced technology nodes.
  • Strong understanding of modern place-and-route flows and implementation methodologies.
  • Experience with full tapeout sign-off, including physical verification, STA, and power integrity.
  • Experience with chip-level floorplanning, hierarchical methodologies, and power grid design.
  • Experience developing constraints, UPF, and high-quality floorplans.
  • Experience with synthesis and providing RTL design input to improve physical QOR.
  • Scripting skills for driving implementation tools and analysing results.
  • Good understanding of the implementation flow from synthesis through silicon sign-off, with specialist expertise in at least one area.
  • Excellent interpersonal and communication skills, and willingness to work on site in Cambridge.

Nice to have

  • Experience with the Cadence implementation tool flow.
  • Experience implementing complex designs.
  • Experience with advanced FinFET technologies.
  • Good understanding of design and front-end processes.

Culture & Benefits

  • Employer pension contribution of 8% when contributing 4% of gross salary through the salary sacrifice scheme.
  • Life assurance of four times base salary.
  • Income protection covering 75% of base salary after 13 weeks of long-term illness or absence.
  • Private medical insurance with medical history disregarded.
  • Electric vehicle salary sacrifice scheme, subject to eligibility.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →