Senior Digital Verification Engineer

TL;DR

Senior Digital Verification Engineer (SystemVerilog/UVM): Verifying functional behavior of complex security-focused digital hardware architectures and building verification plans, strategies, tests, and environments with an accent on coverage closure, constrained-random verification, and SystemVerilog Assertions. Focus on introducing emerging verification methodologies into existing flows and mentoring junior engineers to drive technical excellence across verification teams.

Location: Glasgow, UK

Company

hirify.global develops security hardware IP and end-to-end security solutions across multiple business lines.

What you will do

• Verify functional behavior of complex digital hardware architectures.
• Create, review, and maintain verification plans while tracking verification progress.
• Specify and develop verification strategies, tests, and environments for security features and hardware co-processors.
• Apply emerging verification methodologies and integrate them into existing verification flows.
• Mentor junior team members and drive technical excellence and consistency across teams.

Requirements

• BSc. or MSc. in Electronics or Electrical Engineering.
• Strong hands-on experience with SystemVerilog for testbench development and verification.
• Proven expertise in UVM, including component creation, sequences, drivers, monitors, and scoreboards.
• Solid understanding and practical use of constrained random verification techniques.
• Experience with metrics-driven verification (functional coverage and verification planning) and achieving coverage closure.
• Ability to write SystemVerilog Assertions (SVA) for protocol and design checking.

Nice to have

• Knowledge of formal verification methods.

Culture & Benefits

• Work in a dedicated Crypto & Security Competence Center focused on R&D for future security applications.
• Contribute across the full security hardware product lifecycle, from requirements and architecture through development, verification, and silicon validation.
• Security Design team in Glasgow delivering high-end security IP across multiple market segments.

Hiring process

• Interviews to assess verification experience and technical depth in SystemVerilog/UVM and coverage-driven methodologies.
• Discussion of verification approach, debugging skills, and experience integrating methodologies into existing flows.