1 час назад
Physical Design Engineer (ASIC)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Physical Design Engineer (ASIC): Defining and implementing the physical assembly of SoCs across placement and routing, floorplanning, clocking, timing, electrical analysis, and power with an accent on PPA optimization and deep-submicron 7nm-or-below technologies. Focus on architecting top-level and block-level floorplans, closing timing and power targets, optimizing skew-managed clock trees, and running signoff flows including EM/IR and physical design verification.
Location: Saratoga, CA, United States
Company
is a Silicon Valley hardware startup developing silicon, packaging, software, and systems for high-performance AI data center networking.
What you will do
- Define the physical assembly of SoCs, including placement and routing, timing, floorplanning, clocking, electrical analysis, and power.
- Architect top-level and block-level floorplans and develop synthesis design constraints using SDC.
- Implement designs with Innovus or Synopsys Fusion Compiler, covering synthesis, floorplanning, power planning, and timing closure.
- Work with micro-architects to evaluate feasibility and balance performance, power, and area tradeoffs.
- Develop physical design methodologies and customize implementation recipes to optimize PPA.
- Run and validate signoff flows for timing, power, EM/IR, and physical design verification with a multifunctional engineering team.
Requirements
- 10+ years of experience and a bachelor’s or master’s degree in electrical engineering.
- Experience with synthesis, place-and-route, analysis, verification, and CAD tools.
- Proficiency in Innovus or Synopsys Fusion Compiler, including floorplanning, power planning, and timing closure.
- Experience with multiple tape-outs in deep-submicron technologies at 7nm or below.
- Fluency in Unix, Perl, Python, or TCL scripting, with knowledge of Verilog and SystemVerilog.
- Understanding of device physics, logic and physical design principles, low-power design, and high-performance implementation.
Nice to have
- Experience designing large skew-optimized clock trees such as H-Trees.
- Exposure to clock grid implementation.
Culture & Benefits
- Work with an experienced engineering team focused on AI infrastructure and advanced silicon.
- Contribute to technologies intended to improve AI data center performance, power efficiency, reliability, and deployment speed.
- Compensation is determined based on skills, experience, qualifications, work location, market trends, and comparable employee compensation.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
16 часов назад
Senior Physical Design Engineer (ASIC)
13 часов назад
Physical Design Engineer
200 000 - 400 000$
15 часов назад
Lead Physical Design Engineer (AI Chips)
10 часов назад
Technical Lead Physical Design Engineer (ASIC)
135 000 - 165 000$
17 часов назад
Physical Design Engineer (ASIC)
200 000 - 300 000$
14 часов назад