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Physical Design Engineer (ASIC)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Physical Design Engineer (ASIC): Defining and implementing the physical assembly of SoCs across placement and routing, floorplanning, clocking, timing, electrical analysis, and power with an accent on PPA optimization and deep-submicron 7nm-or-below technologies. Focus on architecting top-level and block-level floorplans, closing timing and power targets, optimizing skew-managed clock trees, and running signoff flows including EM/IR and physical design verification.

Location: Saratoga, CA, United States

Company

hirify.global is a Silicon Valley hardware startup developing silicon, packaging, software, and systems for high-performance AI data center networking.

What you will do

  • Define the physical assembly of SoCs, including placement and routing, timing, floorplanning, clocking, electrical analysis, and power.
  • Architect top-level and block-level floorplans and develop synthesis design constraints using SDC.
  • Implement designs with Innovus or Synopsys Fusion Compiler, covering synthesis, floorplanning, power planning, and timing closure.
  • Work with micro-architects to evaluate feasibility and balance performance, power, and area tradeoffs.
  • Develop physical design methodologies and customize implementation recipes to optimize PPA.
  • Run and validate signoff flows for timing, power, EM/IR, and physical design verification with a multifunctional engineering team.

Requirements

  • 10+ years of experience and a bachelor’s or master’s degree in electrical engineering.
  • Experience with synthesis, place-and-route, analysis, verification, and CAD tools.
  • Proficiency in Innovus or Synopsys Fusion Compiler, including floorplanning, power planning, and timing closure.
  • Experience with multiple tape-outs in deep-submicron technologies at 7nm or below.
  • Fluency in Unix, Perl, Python, or TCL scripting, with knowledge of Verilog and SystemVerilog.
  • Understanding of device physics, logic and physical design principles, low-power design, and high-performance implementation.

Nice to have

  • Experience designing large skew-optimized clock trees such as H-Trees.
  • Exposure to clock grid implementation.

Culture & Benefits

  • Work with an experienced engineering team focused on AI infrastructure and advanced silicon.
  • Contribute to technologies intended to improve AI data center performance, power efficiency, reliability, and deployment speed.
  • Compensation is determined based on skills, experience, qualifications, work location, market trends, and comparable employee compensation.

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