Senior Engineer - Analog Design

Location: Ottawa, Canada; travel required 0%–25%

Annual base salary: 90,000–140,000

Company

hirify.global is a global semiconductor technology company developing products and solutions for timing, communication, and other real-world applications.

What you will do

• Design and simulate analog IP blocks for mixed-signal SoC products.
• Work with design leads to translate circuit requirements into production-ready designs.
• Perform PVT corner analysis and block-level modeling.
• Support silicon validation and laboratory characterization.

Requirements

• PhD or Master's degree in Electrical Engineering; new PhD graduates with relevant experience may apply.
• Approximately 3–5 years of professional experience in analog or mixed-signal IC design.
• Experience with circuits such as PLLs/DLLs, ADCs/DACs, filters, or high-speed I/O.
• Strong analog fundamentals and experience with Cadence IC design tools.
• This is a Senior Engineer individual contributor role and is not aligned to principal-level or system-architecture ownership.

Nice to have

• Research directly applicable to practical analog design.
• Verilog-A modeling experience.
• Scripting or automation experience with Skill, Python, Perl, or Tcl.
• Silicon bring-up or laboratory validation exposure.

Culture & Benefits

• Culture focused on trust, empowerment, respect, diversity, communication, employee development, and community.
• Health benefits begin on the first day.
• Retirement savings plans, restricted stock units, quarterly bonus payments, and an industry-leading IESPP program with a six-month look-back feature.
• Career development is supported through Leadership Passage Programs.