Senior Engineer I - Physical Design

Location: Chandler, Arizona, United States

Company

hirify.global is a global semiconductor company developing microcontrollers, SoCs, and other technologies for embedded applications.

What you will do

• Implement hierarchical, low-power mixed-signal microcontroller and microcontroller-based SoC designs using FLASH process technologies.
• Own physical implementation from design exploration through netlist-to-GDSII delivery and metal-only ECO execution.
• Explore and optimize floorplans, power domains, voltage areas, power grids, placement, routing, and clock distribution.
• Drive timing closure, timing and signal integrity analysis, and optimization at chip and block levels.
• Perform physical verification and reliability sign-off, including DRC, LVS, IR drop, and electromigration analysis.
• Develop physical design flows and methodology while collaborating with synthesis, DFT, IP, CAD, and external vendor teams.

Requirements

• Bachelor's or master's degree in Electrical or Electronic Engineering, or equivalent.
• At least 5 years of hands-on physical design experience with a strong record of project execution.
• Advanced knowledge of place-and-route methodologies and low-power physical design flows.
• Experience with Innovus or Fusion Compiler, Calibre, RedHawk, StarRCXT, or equivalent EDA tools.
• Strong scripting skills in TCL, Perl, and Shell, plus working knowledge of Verilog and VHDL.
• Strong analytical, debugging, communication, and independent project-management skills.

Nice to have

• Familiarity with advanced process nodes.

Culture & Benefits

• Full-time employment within a 17,000-member global organization.
• Employee development through Leadership Passage Programs and other growth initiatives.
• Culture centered on trust, empowerment, respect, diversity, communication, and community.
• Travel requirement of 0%–25%.