Staff Physical Design Engineer - SoC EMIR Engineer

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, including CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Perform IR drop analysis and signal and power electromigration analysis for complex SoCs.
• Develop and execute backend power methodologies for advanced semiconductor chips.
• Collaborate with Physical Design engineers to ensure full power integrity.
• Partner with Package Design engineers on chip-package co-analysis.
• Identify root causes of voltage-drop violations and electromigration risks.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or a related technical field.
• 7+ years of hands-on experience in EMIR or power integrity analysis for high-performance SoCs or high-speed connectivity products.
• Strong proficiency with industry-standard EMIR tools such as Ansys RedHawk, RedHawk-SC, or Cadence Voltus.
• Deep understanding of EM/IR challenges in advanced FinFET nodes, including 7nm, 5nm, and 3nm.
• Deep knowledge of place-and-route flows, power-grid synthesis, RC extraction, standard-cell architecture, and signal versus power-grid electromigration trade-offs.

Nice to have

• Familiarity with thermal analysis tools and their interaction with electrical performance.
• Experience with sign-off criteria and margins for high-volume production chips.
• Good understanding of timing and place-and-route flows.
• Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution.
• Ability to write TCL scripts for STA and Fusion Compiler.

Culture & Benefits

• Opportunity to contribute technical ownership at a newly established strategic R&D center in Israel.
• Work on connectivity silicon supporting large-scale AI and cloud environments.
• Inclusive environment encouraging applications from people with diverse backgrounds and experiences.