3 часа назад
Signal Integrity Senior Engineer (AI Infrastructure)
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Signal Integrity Senior Engineer (AI Infrastructure): Leading SI/PI design and validation for high-speed networking, AI, and data center products operating at 112G and 224G data rates with an accent on PCB and system analysis, channel simulation, laboratory measurement, and simulation-to-measurement correlation. Focus on developing models for packages, connectors, cables, and complete channels, debugging complex signal integrity issues, and defining stackups, routing, via structures, and return paths.
Location: US - Headquarters; on-site
Company
builds high-performance infrastructure for demanding artificial intelligence workloads across silicon, systems, and networking.
What you will do
- Lead signal integrity and power integrity analysis for complex PCB and system designs.
- Define SI/PI architectures, design rules, channel budgets, PCB stackups, routing requirements, via structures, and return path strategies.
- Run pre-layout and post-layout channel simulations and optimize high-speed interfaces using Ansys HFSS, Cadence Clarity, Cadence Sigrity, and Keysight ADS.
- Develop and validate models for packages, PCBs, connectors, cables, backplanes, midplanes, and complete channels.
- Correlate simulations with laboratory measurements, including VNA, TDR/TDT, high-bandwidth oscilloscope, de-embedding, and calibration work.
- Debug signal integrity issues, drive root-cause resolution, mentor engineers, and collaborate with silicon, package, board, mechanical, manufacturing, vendor, and customer teams.
Requirements
- BS or MS in Electrical Engineering or a related field.
- 5+ years of experience in signal integrity, high-speed design, or related areas.
- Strong knowledge of signal integrity, power integrity, electromagnetic theory, transmission lines, high-speed SerDes, PCB and package design, and channel compliance methodologies.
- Extensive hands-on experience with Ansys HFSS, Cadence Clarity, Cadence Sigrity, and Keysight ADS.
- Strong laboratory experience with VNAs, TDR/TDT systems, high-bandwidth oscilloscopes, de-embedding, and calibration techniques.
- Ability to correlate simulations with measured results and drive design improvements.
Nice to have
- Experience with 112G/224G PAM4 SerDes systems.
- Experience with Ethernet, PCIe, UCIe, CXL, DDR, or AI networking products.
- Knowledge of COM, ERL, eye analysis, jitter decomposition, and channel compliance methodologies.
- Experience with Python, MATLAB, or automation frameworks.
- Experience leading SI strategy for large-scale hardware programs.
Culture & Benefits
- Work on foundational infrastructure for next-generation AI workloads.
- Operate in a high-performance environment focused on ownership, technical rigor, and speed.
- Collaborate across silicon, systems, networking, hardware, manufacturing, vendors, and customers.
- Equal opportunity employment and accessibility accommodations are provided throughout the hiring process.
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