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6 часов назад

Staff/ Principal Physical Design Engineer - SoC EMIR Expert (FinFET)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Staff/ Principal Physical Design Engineer - SoC EMIR Expert (FinFET): Developing and signing off EMIR methodologies for complex SoCs powering high-performance AI connectivity systems with an accent on voltage-drop analysis, electromigration, and power integrity. Focus on chip-package co-analysis, root-cause analysis of reliability violations, and ensuring robust power delivery in advanced 7nm, 5nm, and 3nm FinFET processes.

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

  • Perform IR-drop and signal/power electromigration analysis for complex SoCs.
  • Collaborate with Physical Design engineers to ensure full power integrity.
  • Define IR architecture supporting timing convergence and own EMIR methodologies.
  • Partner with Package Design engineers on chip-package co-analysis.
  • Investigate root causes of voltage-drop violations and EM risks.
  • Serve as the technical owner for IR-related issues throughout the project lifecycle.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering or a related technical field.
  • 10+ years of hands-on EMIR or Power Integrity experience with high-performance SoCs or high-speed connectivity products.
  • Strong proficiency with Ansys RedHawk/RedHawk-SC or Cadence Voltus.
  • Deep knowledge of EM/IR challenges in advanced FinFET nodes, including 7nm, 5nm, and 3nm.
  • Experience with Place & Route flows, power-grid synthesis, RC extraction, standard-cell architecture, and EMIR trade-offs.
  • Proficiency in thermal analysis, self-heating, and Statistical EM, with the ability to identify issues early in the project lifecycle.

Nice to have

  • Experience with sub-N5 TSMC technologies and thermal-analysis tools.
  • Experience with sign-off criteria and margins for high-volume production chips.
  • Knowledge of timing, P&R, packaging, top-metal layers, MIM capacitors, and power distribution.
  • Understanding of ESD, including full CDM closure, latch-up, and semiconductor reliability.
  • Ability to write TCL scripts for STA and Fusion Compiler.

Culture & Benefits

  • Join a new strategic R&D center in Israel focused on complex semiconductor chips for AI infrastructure.
  • Work in a diverse engineering environment that encourages creativity, innovation, and varied backgrounds and experiences.

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