Clocking Architect (FPGA/SoC)

Location: San Jose, California, United States. Flexible hybrid work model. The role is tied to the United States and requires eligibility for any required U.S. export authorizations.

Salary: $187,000–$270,700 USD per year for the Bay Area, California.

Company

hirify.global is an independent FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge applications.

What you will do

• Own full-chip and subsystem clocking architectures for next-generation FPGA and SoC devices, including clock topology, domain partitioning, frequency planning, PLL/DLL allocation, clock gating, and dynamic frequency scaling.
• Define clocking for PCIe, DDR5/LPDDR5/HBM, ARM, Ethernet, configuration interfaces, and SerDes, including reference clocks, PLLs, CDRs, jitter budgets, and high-speed protocol timing.
• Architect multi-frequency clock planes for FPGA- and SoC-integrated AI/ML accelerators, memory subsystems, host interconnects, and control paths.
• Own full-chip CDC planning and verification, including synchronizer strategies, metastability budgets, waiver management, and tapeout sign-off.
• Author and maintain functional and DFT SDC constraints for generated clocks, clock exceptions, scan, ATPG, OCC, MBIST, and LBIST, partnering with STA teams on timing closure.
• Lead architecture reviews and cross-functional integration with RTL, physical design, timing, verification, DFT, IP, and external vendor teams while mentoring engineers.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12+ years of industry experience in physical design, SoC/FPGA design, or clocking architecture, including silicon tape-outs at 7nm or below.
• Full-chip and subsystem-level clocking architecture ownership for complex SoC or FPGA devices.
• Expertise in PCIe Gen4/5/6, DDR5, LPDDR5, HBM, ARM CoreLink/CMN, Ethernet, configuration interfaces, and SerDes clocking.
• Expert-level CDC architecture, CDC verification with SpyGlass CDC, JasperGold CDC, or Questa CDC, and SDC authoring with PrimeTime and/or Tempus.
• Comprehensive DFT clocking and low-power design experience, including scan, ATPG, OCC, MBIST, LBIST, UPF/CPF, clock gating, and multi-voltage domains.

Nice to have

• FPGA programmable-logic experience with PLLs, global/regional clock networks, and hard IP subsystems.
• AI/ML FPGA overlay experience, including tensor or matrix engine clocking and dataflow clock-domain partitioning.
• Formal CDC verification, PLL/DLL characterization, jitter analysis, SSC validation, and multi-die or chiplet clocking experience.
• Tcl or Python scripting for constraint automation, CDC report parsing, and custom analysis flows.
• Familiarity with Intel/hirify.global FPGA families such as Stratix and Agilex.

Culture & Benefits

• Engineering-first environment with direct influence on chip architecture decisions.
• Flexible hybrid work model.
• Medical, dental, and vision coverage.
• 401(k) with company match and paid parental leave.
• Professional development investment, advanced EDA infrastructure, IP libraries, and process-node programs.