Senior Pre-Silicon Verification Engineer (Semiconductors)

TL;DR

Senior Pre-Silicon Verification Engineer (Semiconductors): Developing comprehensive verification strategies for digital and mixed-signal IP blocks with an accent on UVM, real number modeling, and AMS simulation. Focus on building scalable verification environments, executing system-level simulations, and debugging complex analog-digital interactions to ensure design quality before fabrication.

Location: Must be based in the greater metropolitan area of Toronto, Ontario. The role is currently remote but will transition to a hybrid model (4 days/week on-site) once the local office is operational.

Salary: CAD 153,910–217,280

Company

hirify.global is a global leader in semiconductor innovation, creating technology that powers the cloud, IoT, and 5G connectivity to solve global challenges.

What you will do

• Perform functional verification of digital and mixed-signal logic components using UVM and advanced modeling techniques.
• Develop comprehensive IP verification plans, test benches, and scalable environments for mixed-signal microarchitecture.
• Execute system-level simulations, analyze power/timing metrics, and conduct corner case analysis.
• Debug complex issues in the pre-silicon environment and implement corrective measures.
• Collaborate with architects, RTL developers, and physical design teams to meet performance and power goals.
• Document test plans and drive technical reviews to maintain verification methodology.

Requirements

• Must be based in the greater metropolitan area of Toronto, Ontario.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM field.
• 5+ years of experience in digital or mixed-signal design verification.
• 3+ years of experience with Pre-Silicon Verification environment architecture and development.
• Proficiency in digital verification methodologies including UVM and SystemVerilog.
• Experience with scripting languages such as Python or Perl.

Nice to have

• Master's degree in Electrical or Computer Engineering.
• Experience with mixed-signal designs like SerDes or PLLs.
• Knowledge of Gate Level Simulation (GLS) and DFT/ATE concepts.
• Experience driving verification methodology changes.

Culture & Benefits

• Competitive salary and comprehensive benefits package.
• Access to cutting-edge verification tools and simulation infrastructure.
• Opportunity to work on advanced mixed-signal designs and technologies.
• Professional development and collaboration with world-class engineering teams.