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8 часов назад

VLSI Design Verification Engineer_1

Тип работы
fulltime
Английский
b2
Страна
Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
VLSI Design Verification Engineer_1 (SystemVerilog/UVM): Developing and executing verification plans, testbenches, assertions, and coverage models for complex SoCs and IPs with an accent on advanced verification methodologies and AI-assisted tools. Focus on debugging cutting-edge silicon designs, ensuring correctness and reliability, and collaborating with architects, designers, and post-silicon teams.

Location: Hsinchu, Taiwan

Company

hirify.global develops AI vision processors for edge applications that extract valuable data from high-resolution video streams.

What you will do

  • Develop and execute verification plans for complex SoCs and IPs.
  • Build testbenches, assertions, and coverage models.
  • Apply SystemVerilog/UVM, coverage-driven, and assertion-based verification methodologies.
  • Collaborate with architects, designers, and post-silicon teams.
  • Ensure the correctness and reliability of advanced silicon designs.

Requirements

  • Bachelor’s, Master’s, or PhD in electrical engineering, computer science, or a related field.
  • Strong background in digital design and computer architecture.
  • Experience with SystemVerilog, UVM, Verilog, C, and C++.
  • Strong debugging, analytical, and problem-solving skills.

Nice to have

  • Perl or Python scripting experience.
  • Experience with AI-assisted verification tools and flows.

Culture & Benefits

  • Work on next-generation SoCs and AI-powered verification flows.
  • Collaborate with global engineers on semiconductor innovation.
  • Learning-driven environment supporting accelerated professional growth.

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