Junior Design Verification Engineer (ASIC)

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor connectivity solutions and software for rack-scale AI infrastructure.

What you will do

• Contribute to ASIC verification environments for unit-level and subsystem digital blocks.
• Develop and maintain SystemVerilog/UVM components, including traffic generators, monitors, and checkers.
• Execute verification plans and develop tests for complex digital designs.
• Implement functional coverage models, analyze gaps, and support verification closure.
• Debug hardware issues, identify root causes, and collaborate with design engineers on resolutions.
• Contribute to verification methodologies and best practices in the Israel R&D center.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Strong understanding of digital logic and at least one programming language: C, C++, or Python.
• Basic familiarity with Verilog or SystemVerilog through academic projects or lab work.
• Fluent Hebrew and English required, with the ability to work effectively in a team.
• Strong attention to detail, curiosity, and interest in finding and resolving bugs.

Nice to have

• Master’s degree in Electrical Engineering or a related field.
• Python or Tcl scripting for verification automation.
• Exposure to UVM, OVM, or constrained-random verification.
• Basic understanding of PCIe, Ethernet, or DDR protocols.

Culture & Benefits

• Opportunity to contribute to a new strategic R&D center in Israel.
• Work on connectivity technologies supporting large-scale AI infrastructure.
• Collaborative, fast-paced, and team-oriented engineering environment.
• Inclusive workplace that encourages applications from candidates with diverse backgrounds and experiences.