Staff/Senior QPU Layout Engineer (Quantum Computing)

Location: London, UK

Company

hirify.global is a quantum computing startup developing scalable silicon-based quantum computers through interdisciplinary research and engineering.

What you will do

• Implement block-level and full-chip physical layouts for silicon spin-qubit SiMOS quantum dots through integration and tapeout.
• Drive layouts to completion using industry-standard EDA tools and practices focused on manufacturability and scalability.
• Deliver designs meeting DRC, LVS, ERC, and other physical verification and sign-off criteria, owning tapeout readiness.
• Interpret electromagnetic analysis and optimise layouts for signal integrity, reliability, and integration.
• Create or adapt schematics and netlists to support LVS and verification flows, and contribute to PDKs, methodologies, and layout conventions.
• Lead design reviews and tapeout planning while collaborating with experimentalists, device modellers, designers, and other engineering disciplines.

Requirements

• Master’s degree in Engineering, Physics, or a related field, or equivalent professional experience.
• 6+ years of experience leading chip layouts through tapeout in research-driven or novel technology environments.
• Strong proficiency with Cadence Virtuoso for full-chip and block-level layout and verification.
• Strong understanding of layout verification using Calibre or an equivalent tool, including DRC, LVS, and ERC.
• Experience interpreting EM simulation results and making engineering sign-off decisions when process rules are evolving or incomplete.
• Track record of effective cross-functional collaboration across disciplines.

Nice to have

• Experience with quantum devices, CMOS process integration, or 3D integration.
• Experience developing PDKs or rule decks, or working with EDA teams.
• Scripting or automation experience with SKILL, Python, or similar tools.
• Experience managing a small team of layout engineers.

Culture & Benefits

• Collaborative, interdisciplinary work across quantum engineering, IC engineering, theory, and software.
• Research and development environment focused on scalable silicon quantum computing.
• Competitive salary and share options scheme.
• Contributory pension scheme and group private medical insurance.
• Life assurance.