13 часов назад
Senior Mask Layout Engineer (Quantum Computing)
126 887 - 166 127$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Mask Layout Engineer (Quantum Computing): Creating Python-based full-reticle mask tapeouts and layout libraries for trapped-ion quantum computers with an accent on photonic and analog electronic layers, physical verification, and semiconductor foundry workflows. Focus on developing PDKs and automated layout tools, implementing DRC/LVS checks, and coordinating complex tapeouts with design, testing, packaging, and foundry teams.
Location: Hybrid/onsite at the College Park, Maryland or Bothell, Washington campuses, United States. Travel up to 10%.
Salary: $126,887–$166,127 approximate annual base salary, plus bonus and equity.
Company
develops integrated quantum computing, networking, sensing, and security platforms, including trapped-ion quantum computers.
What you will do
- Own full-reticle tapeouts for trapped-ion quantum computers, including photonic and analog electronic layers.
- Conduct Python-based layout work with commercial foundries.
- Develop and maintain internal PDKs, PCells, and automated circuit layout libraries.
- Implement physical verification checks, including DRC and LVS.
- Define layout rules and component designs with designers, test engineers, packaging engineers, and foundry teams.
- Document tapeouts, lead layout reviews, and improve design, layout, and testing workflows.
Requirements
- Bachelor’s degree in Photonics, Physics, Electrical Engineering, or a related field, or equivalent practical experience.
- Knowledge of semiconductor manufacturing processes and techniques.
- Strong programming and software skills, including IDE development, version control, shell scripting, and code documentation.
- At least 2 years of experience with Python-based mask layout software such as Luceda IPKISS, GDSFactory, or KLayout.
- Ability to work at the College Park or Bothell campus in a hybrid/onsite arrangement.
- Employment requires meeting U.S. export-control and government-contract eligibility requirements, including U.S. Person status or applicable authorization.
Nice to have
- M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or a related field.
- Five or more years of experience generating layout files for complex semiconductor flows involving MEMS, integrated photonics, or superconducting circuits.
- Experience owning commercial-foundry full-reticle tapeouts and using Synopsys, Cadence, or Ansys environments.
- Knowledge of photonic or analog electronic device design, testing, and fabrication.
- Experience with DRC, LVS, ERC, tapeout workflows, technical documentation, and independent deadline-oriented work.
Culture & Benefits
- Autonomy, productivity, respect, and an inclusive work environment.
- Medical, dental, and vision insurance.
- Matching 401(k), unlimited PTO, and paid holidays.
- Parental and adoption leave, legal insurance, and a home technology stipend.
- Additional compensation through bonus and equity.
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