Staff Digital Design Engineer (PHY)

Location: On-site Monday–Friday in the Bay Area, Vancouver, or Toronto.

Company

hirify.global is an early-stage chiplet startup developing NuLink, a chiplet interconnect platform for next-generation chiplet-based AI and HPC systems.

What you will do

• Lead D2D PHY digital design from microarchitecture definition through synthesis and physical-design handoff.
• Design data-path and clocking architectures for UCIe-compliant advanced-package PHYs, including link training, calibration, rate adaptation, CDC, FIFO alignment, and lane deskew.
• Create microarchitecture specifications, power analyses, latency metrics, performance characterization, SDC constraints, UPF specifications, and synthesis-ready netlists.
• Optimize area, timing, power, and QoR while establishing LINT and CDC flows, rulesets, and waiver management.
• Coordinate with analog PHY, verification, physical-design, and firmware teams on TX/RX controls, PLL and calibration, coverage, placement, clocking, routing, register interfaces, and link-training sequences.
• Mentor 2–3 digital designers and lead design reviews and cross-team technical decisions.

Requirements

• 8+ years of digital frontend design experience, including 4+ years in PHY or high-speed interfaces.
• 3+ successful tapeouts as a design lead in advanced nodes of 7nm or below.
• Deep expertise in D2D PHY, DDR PHY, or SerDes digital design.
• Expert SystemVerilog RTL design and strong synthesis optimization skills.
• Strong understanding of UCIe or other high-speed interfaces such as DDR or SerDes.
• Advanced CDC design, link-training protocols, and elastic-buffer architectures.
• Hands-on experience with Synopsys DC/Fusion Compiler or Cadence Genus.
• Experience with SDC constraints, UPF, and STA methodology.
• Proven ability to lead frontend design and coordinate across teams.

Nice to have

• 12+ years of experience with demonstrated technical leadership.
• UCIe PHY design or certification experience.
• DDR4, DDR5, LPDDR PHY, or DFI interface experience.
• SerDes digital control, including TX/RX equalization and CDR, or PCIe PHY or CXL PHY experience.
• Advanced packaging knowledge including 2.5D, 3D, and organic substrates.
• Firmware development for PHY control or low-level driver implementation.
• Python, Perl, or Tcl scripting for design automation.
• Publications or patents in PHY design.

Culture & Benefits

• Fast-paced early-stage startup environment.
• Fun work environment with excellent benefits.
• On-site work from Monday through Friday.
• Work on chiplet technologies focused on power, area, manufacturability, and design flexibility.