9 часов назад
Staff Digital Design Engineer - PHY
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Staff Digital Design Engineer - PHY (D2D PHY/UCIe): Leading the frontend design of a digital D2D PHY for a chiplet interconnect platform, from microarchitecture through synthesis and physical-design handoff, with an accent on RTL, clocking, link training, calibration, and synthesis optimization. Focus on designing advanced multi-clock PHY architectures, creating SDC and UPF specifications, solving CDC and timing challenges, and coordinating integration across analog, verification, physical-design, and firmware teams.
Location: Bay Area, Vancouver, or Toronto; onsite Monday–Friday
Company
is an early-stage chiplet startup developing NuLink, a chiplet interconnect platform for next-generation AI and HPC systems.
What you will do
- Lead D2D PHY digital design from microarchitecture definition through synthesis and physical-design handoff.
- Design data-path and clocking architectures for UCIe-compliant advanced-package PHYs.
- Develop SystemVerilog RTL for link training, calibration, rate adaptation, CDC, FIFO alignment, and lane deskew.
- Optimize designs for power, performance, area, timing, and synthesis quality of results.
- Create SDC constraints, UPF power specifications, and LINT/CDC flows for multi-clock designs.
- Coordinate with analog, verification, physical-design, and firmware teams while mentoring 2–3 digital designers and leading design reviews.
Requirements
- 8+ years of digital frontend design experience, including 4+ years with PHY or high-speed interfaces.
- Three or more successful tapeouts as a design lead in advanced nodes, 7 nm or below.
- Deep expertise in D2D PHY, DDR PHY, or SerDes digital design.
- Expert SystemVerilog RTL design and synthesis optimization skills.
- Strong understanding of UCIe or comparable high-speed interfaces such as DDR or SerDes, plus CDC design, link-training protocols, and elastic-buffer architectures.
- Hands-on experience with Synopsys DC/Fusion Compiler or Cadence Genus, SDC, UPF, and STA methodologies.
Nice to have
- 12+ years of experience with demonstrated technical leadership.
- UCIe PHY design or certification experience.
- DDR4, DDR5, LPDDR, DFI, PCIe, CXL, or SerDes digital-control experience.
- Advanced packaging knowledge, including 2.5D, 3D, or organic substrates.
- PHY-control firmware or low-level driver development, Python/Perl/Tcl scripting, or PHY-design publications and patents.
Culture & Benefits
- Fast-paced early-stage startup environment.
- Hands-on technical leadership role with cross-functional ownership.
- Fun work environment with excellent benefits.
- Regular onsite collaboration from Monday through Friday.
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