Low-Power Design and Verification Engineer

Location: Palo Alto Office, USA

Company

hirify.global develops world models and AI agents for understanding and building hardware, electronics systems, and semiconductors.

What you will do

• Define power architecture and write UPF power intent for SoCs and IP.
• Implement and verify power gating, clock gating, multi-voltage domains, and retention.
• Run power-aware simulation, static low-power checks, and CDC/RDC analysis.
• Partner with RTL, physical design, and signoff teams on power estimation and closure.
• Build automation for power analysis and reporting.
• Evaluate AI-generated power intent and help define correctness criteria.

Requirements

• 5+ years of low-power design or verification experience on production tapeouts.
• Expert knowledge of UPF and experience with power-aware verification.
• Hands-on experience with VC LP, Conformal Low Power, PowerArtist, or similar tools.
• Experience with CDC/RDC tools such as SpyGlass, Questa CDC, or similar.
• Python or Tcl scripting experience.

Nice to have

• Experience with mobile, edge, or data-center power management.
• Experience with formal verification of power intent.
• Interest in AI-assisted design tools.

Culture & Benefits

• Full-time role based in the Palo Alto office.
• Work with semiconductor companies on real silicon programs.
• Collaborate with a team of semiconductor, hardware, AI, and formal-verification experts.
• Contribute to AI-assisted, power-aware hardware design.