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4 дня назад

Senior Serdes System Design Engineer/Architect

143 800 - 230 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior Serdes System Design Engineer/Architect (DSP/SerDes): Designing and validating high-speed SerDes physical-layer architectures and signal-processing algorithms for 100G+ communication products with an accent on adaptive equalization, FEC, digital filters, and analog integration. Focus on developing bit-exact MATLAB and C/C++ models, running system-level simulations, matching vectors with RTL, debugging firmware, and validating designs in the lab.

Location: USA-TX-Austin - River Place B7

Annual base salary: USD 143,800–230,000, plus discretionary annual bonus and equity awards.

Company

hirify.global develops high-speed SerDes products within its Physical Layer Products Division for advanced wireline communications.

What you will do

  • Develop channel models and run simulations to define high-speed SerDes architectures.
  • Define signal-processing block requirements, architectures, and laboratory test plans.
  • Build bit-exact MATLAB and C/C++ system models and system-level simulation suites.
  • Collaborate with analog and digital design teams on implementation in advanced silicon technology nodes.
  • Perform RTL vector-matching verification, develop and debug physical-layer firmware, and validate SerDes designs in the laboratory.
  • Support standards development, documentation, application notes, customer meetings, and technical collateral.

Requirements

  • B.S.E.E. with 12+ years of relevant experience or M.S.E.E. with 10+ years of relevant experience.
  • Expert knowledge of communication theory and digital signal-processing algorithms.
  • Working knowledge of analog circuit behavior, transmission-line theory, and S-parameters.
  • Expert-level MATLAB and C/C++ programming skills.
  • Hands-on laboratory testing and debugging experience.
  • Knowledge of IEEE 802.3/OIF 100G/200G/400G SerDes or PCIe Gen6/Gen7 standards is an advantage.

Nice to have

  • Experience designing high-speed Clock and Data Recovery PLLs.
  • Experience with equalization techniques for wireline communications, including read-channel applications.
  • RTL coding experience.

Culture & Benefits

  • Full-time employment with medical, dental, and vision plans.
  • 401(k) participation with company matching and an Employee Stock Purchase Program.
  • Discretionary annual bonus, competitive new-hire equity grants, and annual equity awards.
  • Paid holidays, sick leave, vacation time, and applicable paid family leave.
  • Employee Assistance Program and support for other legally applicable leaves of absence.

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