Senior Serdes System Design Engineer/Architect (DSP/Systems Design): Designing and validating high-speed 100G+ Serdes physical-layer signal-processing algorithms, architectures, and system models with an accent on adaptive equalization, FEC, modulation, digital filtering, and analog non-ideality compensation. Focus on developing bit-exact MATLAB and C/C++ models, defining architecture and lab test plans, debugging firmware and Serdes in the lab, and supporting next-generation IEEE and OIF wireline standards.
Location: USA-TX-Austin - River Place B7; onsite role.
Annual base salary: USD 143,800.00–230,000.00. Additional discretionary annual bonus and equity awards may be available.
Company
hirify.global develops high-speed Serdes products and physical-layer solutions for wireline communications.
What you will do
Develop channel models, run system-level simulations, and define Serdes architectures for 100G+ products.
Define and document signal-processing block requirements, architectures, and laboratory test plans.
Develop bit-exact MATLAB and C/C++ system models for simulation and verification.
Collaborate with analog and digital designers on implementation in advanced silicon technology nodes and perform vector-matching verification with RTL simulations.
Develop, test, and debug physical-layer firmware; conduct laboratory testing and debug of Serdes.
Support IEEE and OIF standards work, documentation and application-note development, customer support, and customer-facing marketing activities.
Requirements
B.S.E.E. with 12+ years of relevant experience or M.S.E.E. with 10+ years of relevant experience.
Expert knowledge of communication theory and digital signal-processing algorithms.
Working knowledge of analog circuit behavior, transmission-line theory, and S-parameters.
Expert proficiency in MATLAB and C/C++ programming.
Good hands-on laboratory skills.
Nice to have
Experience designing high-speed Clock and Data Recovery PLLs.
Experience with equalization techniques for wireline communication applications such as read-channel systems.
RTL coding experience.
Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards.
Culture & Benefits
Medical, dental, and vision plans.
401(k) participation with company matching and an Employee Stock Purchase Program.
Employee Assistance Program, company-paid holidays, paid sick leave, vacation time, and applicable paid family leave and other leaves of absence.
Discretionary annual bonus, competitive new-hire equity grant, and annual equity awards, subject to plan documents and award agreements.
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