pythonc++test automationcpciesignal integrityserdespost silicon validationsilicon bring up
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$207к-230к/год
$190к$210кмедиана$220к
По похожим ролям (50) ~ $210к/год
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Актуальные технологииИнфраструктура ИИПонятная рольЗарплата по рынку
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Текст:
Hirify AI/Оригинал
TL;DR
Principal Post-Silicon Validation Engineer (PCIe): Leading post-silicon validation of high-speed connectivity silicon from first-silicon bring-up through characterization and production release with an accent on PCIe physical-layer performance, system-level debugging, and scalable automation. Focus on characterizing serial links across process, voltage, and temperature, solving hardware and firmware failures to root cause, and building Python and C/C++ validation infrastructure.
Location: San Jose, California, United States
Salary: $207,000–$230,000 per year, depending on experience, level, and business need. The role may also be eligible for discretionary bonus, incentives, and benefits.
Company
hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for CXL, Ethernet, NVLink, PCIe, and UALink systems.
What you will do
Architect and drive end-to-end post-silicon validation plans from first-silicon bring-up through characterization and production release.
Define test strategies, coverage goals, and exit criteria with design, architecture, and product teams.
Lead laboratory bring-up of new silicon, including board, firmware, and software readiness.
Debug silicon, firmware, and system-level failures across the hardware/software boundary and drive issues to root cause.
Characterize high-speed serial links, including margining, signal integrity, and compliance across process, voltage, and temperature.
Build validation automation, lab infrastructure, test benches, and data-analysis flows; mentor engineers and collaborate with customers and Field Applications Engineers.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
8–12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization.
Hands-on experience with high-speed serial interfaces such as PCIe and strong understanding of the physical layer.
Proficiency with laboratory equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies.
Strong scripting and programming skills in Python and/or C/C++ for test automation.
Proven ability to debug complex hardware and firmware issues to root cause.
Nice to have
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience with PCIe Gen 5 or Gen 6, Ethernet, or retimer products.
Experience with SerDes characterization, equalization tuning, and link margining.
Track record of taking multiple products from first silicon to volume production.
Strong cross-functional communication skills and the ability to lead without direct authority.
Culture & Benefits
Work in a hyper-growth AI infrastructure company where technical judgment influences product quality, performance, and time-to-market.
Collaborate with hyperscalers, ecosystem partners, design, architecture, product, DFT, customer, and Field Applications Engineering teams.
Discretionary bonus, incentives, and benefits may be available.
The company encourages applications from people with diverse backgrounds and experiences, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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