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5 часов назад

Senior/Staff Analog Design Engineer (SerDes)

317 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK/US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior/Staff Analog Design Engineer (SerDes): Developing high-speed SerDes and mixed-signal subsystems for a next-generation AI accelerator SoC with an accent on serializer, receiver, equalization, clock-generation, and advanced FinFET circuit design. Focus on schematic and post-layout simulation, behavioral and Verilog-A modeling, silicon-margin analysis, and post-silicon lab validation.

Location: On-site in Austin, TX or Bristol, UK

Salary: Starting from $317,000 in Austin or £172,000 in Bristol

Company

hirify.global develops the DX-1 decode accelerator, a rack-scale AI hardware platform combining logic, data movement, packaging, optics, and interconnect.

What you will do

  • Architect and design high-speed SerDes blocks, including serializers, TX drivers, TIAs, CTLEs, CDRs, deserializers, and clock-generation circuits.
  • Take designs from specification through silicon in advanced FinFET nodes, including schematic, post-layout, EM-IR, and reliability simulations.
  • Run EM simulations for passives, package interconnects, and on-die routing; develop behavioral and Verilog-A models for mixed-signal verification.
  • Guide mask designers on floorplanning and layout, and own design reviews and technical documentation.
  • Collaborate with optical, digital, and system teams on interface and link-level performance.
  • Support post-silicon bring-up, laboratory validation, debugging, and correlation of measured data with simulations.

Requirements

  • MS or PhD in Electrical Engineering and 10+ years of analog or mixed-signal IC design experience.
  • Hands-on SerDes design experience at data rates of 25 Gbps or higher.
  • Strong understanding of jitter, noise, equalization, signal integrity, and link budgeting.
  • Expertise in advanced FinFET nodes, device physics, parasitics, and layout-sensitive design.
  • Proficiency with Cadence Virtuoso, Spectre, PVT, Monte Carlo, EM-IR, and reliability analysis flows.
  • Experience with post-silicon bring-up, laboratory measurement equipment, and mixed-signal verification.

Culture & Benefits

  • In-office collaboration in Austin with engineering teams in London and Bristol.
  • Meaningful stock options and ownership participation.
  • Annual Living-Local Bonus for employees living within 20 minutes of the office.
  • Employer-contributed retirement plans.
  • Eligibility is subject to U.S. export control regulations and citizenship or permanent-residency restrictions.

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