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8 дней назад

Digital Signal Processing and System Validation Engineer

120 000 - 192 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Digital Signal Processing and System Validation Engineer (Optical Connectivity): Designing DSP blocks for next-generation optical data center products with an accent on SerDes and high-speed serial links. Focus on pre- and post-silicon validation of ASIC architecture, translating CDR/equalization into Verilog, and optimizing ADC-based interconnects for performance, power, and cost.

Location: USA - California - San Jose (full-time onsite)

Salary: $120,000 - $192,000

Company

Global technology leader designing semiconductors and infrastructure software solutions for data centers and networking.

What you will do

  • Design digital signal processing blocks for optical data center connectivity ASICs.
  • Validate ASIC architecture pre- and post-silicon for SerDes and serial links.
  • Translate CDR, equalization, and analog architectures into synthesizable Verilog code.
  • Optimize designs for high-speed metrics like 100G/200G/400G PAM4/NRZ performance, power, and cost.
  • Perform synthesis, CDC, static timing analysis, and DFT-friendly RTL development.

Requirements

  • MS in Electrical/Computer Engineering with 6+ years or PhD with 3+ years in DSP design for SerDes/high-speed networking
  • Experience in post-silicon validation of mixed-signal IPs
  • Deep knowledge of ADC, optical/electrical interconnects, PAM4/NRZ trade-offs
  • Proficiency in Matlab, Simulink, Verilog-HDL/SystemVerilog
  • Experience with front-end tools (NCVerilog, NCSIM, Simvision, Spyglass), synthesis, CDC, STA
  • Understanding of DFT, scan concepts, parasitic delays in SDF simulations

Nice to have

  • High-speed DSP algorithms, ADC/FFE/DFE/CDR adaptation for PAM4
  • Logic optimization for low power, timing, DFT
  • Signal/Power Integrity modeling, Verilog AMS, behavioral analog models

Culture & Benefits

  • Competitive base salary, annual bonus, equity grants
  • Comprehensive medical, dental, vision; 401(k) with matching, ESPP
  • Paid holidays, sick leave, vacation, family leave
  • Employee Assistance Program (EAP)

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