обновлено 16 часов назад
Digital Signal Processing and System Validation Engineer (SerDes)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Digital Signal Processing and System Validation Engineer (SerDes): Designing digital signal processing blocks for next-generation optical data center connectivity products and validating ASIC architectures before and after silicon with an accent on high-speed SerDes, PAM4/NRZ interconnects, and mixed-signal IP. Focus on translating CDR and equalization architectures into synthesizable Verilog, optimizing performance, power, and cost, and validating designs through synthesis, CDC, timing, and SDF-annotated simulations.
Location: Onsite in San Jose, California, USA
Company
develops connectivity and semiconductor technologies, including optical data center connectivity products.
What you will do
- Design digital signal processing blocks for next-generation optical data center connectivity products.
- Validate ASIC architectures through pre-silicon and post-silicon activities.
- Translate CDR and equalization architectures into synthesizable Verilog code.
- Evaluate ADC-based optical and electrical interconnect architectures, including 100G/200G/400G-per-lane PAM4 and NRZ designs.
- Optimize designs for performance, power, cost, timing margins, and testability.
- Collaborate across technical and management functions to drive project results.
Requirements
- MS in Electrical Engineering or Computer Engineering with 10+ years of relevant experience, or PhD with 7+ years of experience.
- Experience designing digital signal processing solutions for SerDes and high-speed data center networking.
- Experience validating digital and analog mixed-signal IPs after silicon.
- Proficiency with Matlab, Simulink, Verilog-HDL, and SystemVerilog.
- Experience with NCVerilog, NCSIM, Simvision, Spyglass, synthesis, CDC, static timing analysis, and SDF-annotated simulations.
- Understanding of DFT, scan concepts, DFT-friendly RTL, and parasitic delays.
Nice to have
- Experience with high-speed ADC, FFE, DFE, and CDR adaptation algorithms for PAM4 signals.
- Understanding of signal integrity and power integrity modeling for high-speed designs.
- Experience with Verilog-AMS simulation and behavioral models of analog circuits.
- Experience optimizing logic for low power and timing margins.
- Strong communication, collaboration, innovation, and task-management skills.
Culture & Benefits
- Eligibility for a discretionary annual bonus and new-hire and annual equity awards.
- Medical, dental, and vision plans.
- 401(k) participation with company matching and an Employee Stock Purchase Program.
- Employee Assistance Program, paid holidays, paid sick leave, and vacation time.
- Paid family leave and other legally applicable leaves of absence.
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