Analog Design Engineer (SerDes)

Location: Santa Clara, United States; hybrid work

Salary: $155,000–$250,000 per year, plus equity and bonus opportunities

Company

hirify.global develops software and hardware technologies for generative AI.

What you will do

• Own transistor-level design of low-jitter PLLs, DLLs, phase interpolators, and clocking subsystems for high-speed SerDes.
• Design high-frequency clock distribution, duty-cycle correction, quadrature generation, skew control, and supply isolation across the SerDes macro.
• Define and verify CDR architecture and loop dynamics, including bandwidth, jitter tolerance, jitter transfer, lock acquisition, and frequency-offset tracking.
• Build phase-noise and jitter budgets and develop behavioral and Verilog-A models for full-chip verification.
• Lead verification across PVT corners, Monte Carlo, transient noise, PSS/HB, and post-layout simulations.
• Drive block layout, silicon bring-up, and bench characterization, correlating measured phase noise, jitter tolerance, and lock range with simulations.

Requirements

• BS, MS, or PhD in Electrical Engineering and 5+ years of hands-on analog and mixed-signal circuit design experience.
• Demonstrated ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link.
• Deep knowledge of PLL architecture, loop dynamics, VCO design, phase-noise theory, CDR architectures, jitter tolerance, and jitter transfer.
• Experience with advanced FinFET or GAA process nodes and tools such as Cadence Virtuoso, Spectre, Monte Carlo, corner analysis, and post-layout simulation.
• Experience with silicon bring-up and bench debugging using phase-noise analyzers, high-speed oscilloscopes, and BERTs.

Nice to have

• Die-to-die interconnect experience with UCIe, BoW, or proprietary D2D PHYs.
• Experience with forwarded-clock, matched-source-synchronous, digital, and hybrid PLL/CDR architectures.
• Familiarity with UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7, or standards-body participation.
• Experience porting clocking blocks across process nodes.

Culture & Benefits

• Collaborative, inclusive environment centered on respect, humility, direct communication, and execution.
• Medical, dental, and vision coverage.
• 401(k) and rewards tied to individual and company performance.
• Equity and bonus opportunities.