Senior/Staff Digital Design Engineers (CMOS)

Location: On-site in Austin, Texas, or Bristol, UK

Salary: Starting from $194,000 in Austin or £123,000 in Bristol

Company

hirify.global develops the DX-1 decode accelerator, a rack-scale AI hardware platform combining digital logic, data movement, packaging, optics, and interconnects.

What you will do

• Architect and implement high-throughput digital pipelines with multi-GSPS input rates, continuous streaming data paths, deep pipelining, and handshaking in advanced CMOS nodes.
• Prototype designs on Xilinx/AMD, Intel, or equivalent FPGA platforms, including real-time demonstrations, high-speed transceiver bring-up, constraint management, and laboratory debugging.
• Model algorithms in MATLAB/Simulink or Python/NumPy and maintain functional equivalence through RTL, synthesis, gate-level simulation, and sign-off.
• Own RTL development in SystemVerilog, Verilog, or VHDL, including synthesis, static-timing closure, formal verification, and constrained-random verification.
• Analyze and optimize power, performance, and area while integrating data-converter interfaces, clock-domain crossings, and firmware abstractions with optical, mixed-signal, and software teams.
• Lead design reviews, mentor junior engineers, and establish best-practice digital design methodologies.

Requirements

• 7+ years of hands-on digital design experience for high-performance ASICs or SoCs, including ownership of a product processing a continuous real-time data stream.
• Experience closing timing on multi-hundred-MHz to multi-GHz clock domains and integrating high-speed IP such as SerDes, HBM/DDR, PCIe, or 100 GbE.
• Expertise with RTL synthesis, CDC/RDC, STA, UPF/CPF power intent, lint, and gate-level simulation.
• Strong FPGA prototyping skills, including constraint management, transceiver tuning, and hardware debugging in the lab.
• Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modeling, fixed-point analysis, and test-vector generation.
• Solid knowledge of digital signal processing, computer architecture, semiconductor device physics, and cross-functional engineering collaboration.

Nice to have

• Tape-out experience on an advanced process node.
• Knowledge of coherent optical links or photonic-electronic co-design.
• Familiarity with AI/ML workloads, systolic arrays, or tensor-processing architectures.
• Contributions to open-source RTL, verification frameworks, or FPGA boards.

Culture & Benefits

• Meaningful stock options and ownership in the company.
• Employer-contributed retirement plans.
• Annual Living-Local Bonus for employees living within 20 minutes of the office.
• Eligibility to work at hirify.global is subject to U.S. export-control regulations and recent citizenship or permanent-residency status.
• Applicants whose most recent citizenship or permanent residence is in Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, or Venezuela may be restricted from consideration.