Tech Lead Design Engineer (PCIe/CXL)

Location: San Jose, California, United States

Salary: $185,000–$240,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also apply.

Company

hirify.global develops rack-scale AI infrastructure and semiconductor-based connectivity solutions using PCIe, CXL, Ethernet, NVLink, and UALink technologies, supported by its COSMOS software suite.

What you will do

• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
• Develop synthesizable Verilog/SystemVerilog with strong attention to power, performance, and area.
• Drive design reviews, lint, CDC, timing closure, and silicon-readiness activities.
• Translate specifications into implementation-ready microarchitecture and collaborate with verification on test plans, coverage, and bug triage.
• Coordinate with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.
• Mentor junior engineers, improve design methodology, and debug pre-silicon and post-silicon issues.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of digital design experience, including at least one complete chip from specification through tapeout.
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
• Hands-on experience with timing closure, CDC, lint, and low-power design techniques.
• Understanding of high-speed serial interfaces such as PCIe or Ethernet and SoC integration.

Nice to have

• MS or PhD in Electrical Engineering or Computer Engineering.
• Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs.
• Familiarity with formal verification, emulation, or assertion-based methodologies.
• Experience with advanced process nodes such as 7nm, 5nm, or below.
• Strong debugging skills across pre-silicon and post-silicon environments.

Culture & Benefits

• Work on connectivity silicon for large-scale AI infrastructure.
• Collaborate across architecture, verification, DFT, and physical design disciplines.
• Contribute to design methodology, scripts, and engineering best practices.
• Opportunity to work on complex, emerging interconnect technologies.
• Potential eligibility for discretionary bonuses, incentives, and benefits.