Principal DFT Architect

Location: San Jose, California, United States. Applicants must be eligible for any required U.S. export authorizations.

Salary: $209,500–$299,200 USD annually for the Bay Area, California.

Company

hirify.global provides programmable FPGA technologies for AI, cloud, networking, edge, and other rapidly evolving markets.

What you will do

• Define and drive long-term DFT architecture for FPGA, SoC, processor, DSP, SERDES, IO, and multi-die products.
• Develop scalable DFT methodologies and flows across RTL, gate-level, hierarchical, and multi-die integration environments.
• Architect scan, compression, ATPG, MBIST, LBIST, boundary scan, and in-system test solutions.
• Lead DFT planning for 2.5D/3D ICs, chiplets, and heterogeneous multi-die systems.
• Govern DFT specifications, timing constraints, guidelines, and signoff criteria across engineering programs.
• Lead silicon debug, failure analysis, manufacturing test optimization, and technical mentorship.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, with 15+ years of industry experience.
• 10+ years architecting and implementing DFT solutions for complex SoC, FPGA, ASIC, or multi-die designs.
• 10+ years of experience with scan architecture, ATPG, compression, MBIST, LBIST, boundary scan, and hierarchical DFT.
• 10+ years integrating DFT from RTL to GDS, including scan insertion, STA constraints, low-power DFT, and gate-level verification.
• 10+ years with EDA tools, silicon bring-up, manufacturing test flows, yield analysis, failure debug, and DFT automation using Perl, Python, or TCL.
• Eligibility for any required U.S. export authorizations.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with advanced fault models, diagnosis, silicon analytics, 2.5D/3D ICs, chiplets, and high-speed IO/SerDes DFT.
• Familiarity with IJTAG, JTAG, IEEE 1149.x, embedded instrumentation, power-aware DFT, and low-power ATPG.
• Experience developing scalable DFT methodologies incorporating AI technologies.

Culture & Benefits

• Incentive opportunities tied to individual and company performance.
• Collaboration across architecture, RTL, physical design, validation, product engineering, and manufacturing teams.
• Opportunity to influence DFT strategy across multiple product generations and product families.
• Technical leadership and mentorship across large engineering programs.