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6 часов назад

Staff / Principal ASIC Design Engineer

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Staff / Principal ASIC Design Engineer (AI infrastructure connectivity): Designing complex digital ASIC blocks for high-performance semiconductor connectivity solutions, from high-level definition and micro-architecture through RTL implementation and backend support with an accent on PPA optimization, power efficiency, and deep-submicron design. Focus on solving complex logic challenges, applying verification and timing analysis, and improving design methodologies and automation with AI assistance tools.

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

  • Own digital logic blocks from high-level definition and micro-architecture through RTL coding, debugging, and backend implementation support.
  • Design high-performance hardware solutions for complex AI infrastructure connectivity projects.
  • Act as the technical point of contact for assigned logic blocks and collaborate with Architecture, Verification, and Backend teams.
  • Use lint, CDC, synthesis, timing, power, and internal quality-assurance tools to improve design robustness and efficiency.
  • Apply design techniques to meet power, performance, and area targets.
  • Contribute to design methodology improvements, tool automation, verification, validation, and AI-assisted engineering workflows.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related technical field.
  • 5+ years of logic design experience at semiconductor companies.
  • Knowledge and practical experience with Verilog and/or SystemVerilog.
  • Strong understanding of digital design principles and RTL coding best practices.
  • Excellent communication skills and ability to collaborate across engineering teams.

Nice to have

  • Master’s degree in Electrical Engineering or a related field.
  • Experience with DDR and PCIe protocols, high-speed serial interfaces, or connectivity protocols.
  • Knowledge of low-power design and power-management techniques.
  • Familiarity with clock-domain crossing, simulation, debugging, synthesis, and timing analysis.
  • Proficiency in Python or Perl scripting.

Culture & Benefits

  • Opportunity to help establish a strategic R&D center in Israel.
  • Work on semiconductor technologies supporting large-scale AI clusters.
  • Collaborative environment spanning Architecture, Verification, Backend, and other engineering functions.
  • Inclusive workplace that encourages applications from people with diverse backgrounds and experiences.

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