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15 часов назад

DFT Design Engineering Director (2.5D/3D Packaging)

230 000 - 265 000$
Тип работы
fulltime
Грейд
director
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
DFT Design Engineering Director (2.5D/3D Packaging): Defining and executing DFT strategy for PCIe Gen3–6 switch products using complex multi-die architectures with an accent on advanced packaging test access, coverage, yield, and production scalability. Focus on architecting scan, ATPG, MBIST, LBIST, IEEE 1838, SerDes BIST, and pre-bond/post-bond test strategies while leading teams through tape-out and production ramp.

Location: San Jose, California, United States

Base salary: $230,000–$265,000 USD per year

Company

hirify.global provides rack-scale AI infrastructure through semiconductor connectivity solutions and software based on CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

  • Define and lead DFT strategy for PCIe Gen3–6 switch products using 2.5D and 3D packaging.
  • Lead and mentor DFT engineers across multiple product development cycles and tape-outs.
  • Architect multi-die test access, chiplet-level DFT, die-to-die testing, KGD qualification, and pre-bond/post-bond test strategies.
  • Implement scan, ATPG, compression, MBIST, LBIST, JTAG, IJTAG, IEEE 1838, SerDes BIST, analog/mixed-signal test hooks, and BISR.
  • Optimize test coverage, test time, ATE cost, yield, diagnostics, and production test programs.
  • Collaborate with design, verification, physical design, packaging, silicon validation, manufacturing, OSAT, substrate, and ATE partners.

Requirements

  • MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • 12+ years of DFT engineering experience with complex SoC or ASIC products and 5+ years in technical leadership or management.
  • 5+ years of hands-on experience with 2.5D and/or 3D packaging DFT strategies.
  • Experience taking multi-die products from design through production ramp and a record of successful high-volume tape-outs.
  • Expertise with DFT methodologies, DFT EDA tools, ASIC RTL-to-GDS flows, SerDes testing, ATE platforms, yield analysis, and production test economics.
  • Experience with IEEE 1149.1, IEEE 1687, and IEEE 1838 standards, plus the ability to lead teams and work with external packaging and manufacturing partners.

Nice to have

  • Experience with PCIe, CXL, networking, switch products, or high-speed serial protocols.
  • HBM testing, chiplet architectures such as UCIe, BoW, or AIB, and advanced 3D bonding technologies.
  • Wafer-level testing, probe strategies, thermal and power integrity, DTCO, functional safety, automotive quality, or machine-learning-based test optimization.

Culture & Benefits

  • Base compensation is determined by location, experience, and comparable employee compensation.
  • Work involves collaboration across design, packaging, manufacturing, validation, and external technology partners.
  • The company encourages applications from people with diverse backgrounds and experiences.

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