8 часов назад
Design Verification Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Design Verification Engineer (SystemVerilog/UVM): Defining and implementing block- and system-level verification strategies for hardware designs with an accent on test planning, verification infrastructure, and coverage closure. Focus on building UVM and Python-based environments, debugging functional failures, and verifying high-speed interfaces and ARM/RISC-V-based subsystems.
Location: Seoul HQ, Seoul, South Korea
Company
develops AI hardware and related computing technologies.
What you will do
- Define, plan, and implement block- and system-level verification strategies.
- Write and review test plans, and develop test harnesses and test sequences.
- Drive verification to closure across test-plan metrics, functional coverage, and code coverage.
- Collaborate with Design teams to debug, identify root causes, and resolve functional failures.
- Work with Design, Model, Emulation, and Silicon Validation teams to ensure design quality.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Science, or a closely related technical field.
- 5+ years of experience in block- and system-level verification using SystemVerilog and UVM-based methodologies.
- Experience with EDA tools and scripting languages including Python, Perl, and Shell.
- Experience architecting and deploying design verification infrastructure through the complete verification cycle, from planning to closure.
- Strong written and verbal communication skills.
Nice to have
- Master’s degree in Electrical Engineering, Computer Science, or a closely related technical field.
- Expertise developing UVM-based verification environments from initial setup.
- Expertise developing Python-based verification environments such as cocotb.
- Experience verifying high-speed interfaces including PCIe, UCIe, UALink, and Ethernet.
- Experience verifying ARM- or RISC-V-based subsystems or SoCs.
Culture & Benefits
- Full-time position within the Hardware Verification department.
- Cross-functional collaboration across hardware design, modeling, emulation, and silicon validation.
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