Senior Design Verification Engineer (ASIC)

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

• Design and develop ASIC verification environments for unit-level and subsystem functional blocks.
• Develop and maintain SystemVerilog/UVM components, including traffic generators, monitors, and checkers.
• Execute verification plans for complex digital designs and implement functional coverage models.
• Analyze coverage results, identify verification gaps, and drive designs toward verification closure.
• Debug complex hardware issues with design engineers and contribute to verification methodology improvements.

Requirements

• Bachelor’s degree in Electrical Engineering or a related technical field.
• 3+ years of ASIC verification experience in the semiconductor industry.
• Hands-on experience developing complex verification environments using SystemVerilog.
• Strong knowledge of UVM and standard verification methodologies.
• Strong analytical, debugging, communication, and cross-functional collaboration skills.

Nice to have

• Master’s degree in Electrical Engineering or a related field.
• Experience with formal verification or emulation flows.
• Python or Tcl scripting for verification automation.
• Exposure to AMBA, PCIe, Ethernet, or CXL protocols.
• Experience with assertion-based verification, constrained-random testing, or connectivity and networking silicon.

Culture & Benefits

• Opportunity to join a new strategic R&D center in Israel and take ownership of its engineering development.
• Collaborative, team-oriented environment working on next-generation AI infrastructure connectivity.
• Inclusive workplace encouraging applications from people with diverse backgrounds and experiences.