Senior Staff ASIC Design Engineer (Semiconductors)

TL;DR

Senior Staff ASIC Design Engineer (ASIC/SOC): Designing and implementing high-performance Ethernet and data path cryptography solutions for 3nm SOCs with an accent on RTL design and hardware security. Focus on writing Verilog code, resolving complex timing and CDC issues, and collaborating with cross-functional teams to deliver leading-edge semiconductor products.

Location: Ottawa, Canada

Salary: 118,700 - 158,300 CAD per annum

Company

hirify.global provides semiconductor solutions for data infrastructure, cloud, and AI architectures.

What you will do

• Design RTL code in Verilog for IPs, subsystems, or SOCs.
• Develop clear technical specifications and comprehensive test plans for design blocks.
• Execute RTL lint, block-level assertions, code coverage closure, CDC, and timing closure.
• Debug complex design issues using industry best practices and write necessary scripts.
• Collaborate with architects, verification, physical design, and software/firmware engineers.
• Provide front-line technical support to internal and external customers.

Requirements

• Bachelor's degree in CS, Electrical Engineering or related (5+ years exp) OR Master's/PhD (3+ years exp).
• Proficiency in Verilog/System Verilog and semiconductor ASIC design methodologies.
• Strong working knowledge of digital logic and computer architecture.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Nice to have

• Knowledge of Ethernet and datapath cryptographic algorithms.

Culture & Benefits

• Collaborative, transparent, and inclusive work environment.
• Competitive compensation package with comprehensive benefits.
• Focus on purposeful innovation and long-term professional growth.

Hiring process

• Interviews designed to evaluate individual experience, thought process, and communication.
• AI tools (ChatGPT, Copilot, etc.) are strictly prohibited during interviews and will lead to disqualification.