Technologist, Hardware Development Engineering

Location: Onsite at the Roseville, California office, United States

Salary: $170,600–$227,400 annually

Company

hirify.global develops large-scale data storage systems and manufacturing solutions for hyperscale data centers, cloud platforms, and enterprise infrastructure supporting the AI-driven data economy.

What you will do

• Own complex hardware programs from architecture and schematic design through build, bring-up, debug, qualification, production ramp, and sustaining.
• Design and integrate board-level hardware, ASIC I/O, packages, substrates, power domains, and high-speed channels.
• Develop and debug 100G/200G Ethernet PAM4 and PCIe Gen 6 interfaces, including equalization, BER/PRBS testing, standards compliance, and link validation.
• Lead FPGA-based platform bring-up from first power-on through transceiver validation, link training, and system integration.
• Analyze and optimize signal integrity, power integrity, EMI/EMC, clocking, reset, thermal, and manufacturability constraints across die, package, PCB, connectors, and cabling.
• Create EVT test plans, correlate simulation with high-speed laboratory measurements, identify root causes, and drive corrective actions.

Requirements

• Professional hardware engineering experience and ownership of multiple complex programs across the full product lifecycle.
• Hands-on expertise in both board/system hardware design and ASIC I/O and integration.
• Expertise with high-speed Ethernet, PCIe, FPGA platforms, SI/PI modeling, controlled-impedance design, and lab validation.
• Experience with multi-rail power distribution, clocking and reset architectures, analog and mixed-signal circuits, package effects, and manufacturing constraints.
• Working knowledge of JTAG/boundary scan, scan/ATPG, BIST, loopbacks, PRBS, on-chip monitoring, and board-to-manufacturing test strategies.
• Experience with schematic/layout tools such as Cadence, Altium, or Mentor-class environments, plus IBIS/AMI, S-parameter, and SPICE-based workflows.

Nice to have

• AMD FPGA experience.
• Advanced packaging or multi-die systems, including chiplets, interposers, or HBM-class integration.
• Ownership of EMC, safety, thermal, or mechanical qualification and production-yield improvements.
• Experience with cost reduction, second-source strategies, and field reliability initiatives.

Culture & Benefits

• Cross-functional technical leadership across silicon, package, board, validation, test, and manufacturing teams.
• Mentoring engineers and leading design reviews focused on early risk identification.
• Paid vacation and sick leave.
• Medical, dental, vision, life, accident, and disability insurance, plus flexible spending and health savings accounts.
• Tuition reimbursement, transit benefits, employee stock purchase plan, 401(k), and potential incentive or long-term equity programs.