Senior Quantum Engineer, Gate Calibration

Location: Berkeley, CA; hybrid workplace

Company

hirify.global develops tunable-coupler superconducting quantum processors and quantum computing hardware and software.

What you will do

• Lead experiments to characterize, calibrate, and optimize two-qubit gates from individual qubit pairs through full-processor deployment.
• Identify and isolate coherent control errors, decoherence, leakage, crosstalk, TLS interactions, and other gate-error sources through experiments, benchmarking, and simulation.
• Develop robust and automated calibration methods using optimal pulse shaping, dynamical decoupling, and other error-suppression strategies.
• Improve full-processor Hamiltonian and characteristic extraction, correlate metrology with gate performance, and provide actionable feedback to device design, fabrication, and control hardware teams.
• Prepare novel hirify.global devices for internal applications development and external deployment.
• Translate state-of-the-art techniques and research findings into production capability and high-quality publications.

Requirements

• PhD in Physics, Applied Physics, Electrical Engineering, or a related field.
• Significant hands-on experience calibrating and characterizing two-qubit gates on superconducting quantum devices. Direct tunable-coupler experience is advantageous.
• Deep understanding of gate design, pulse engineering, and decoherence mechanisms, with experience connecting error diagnostics to concrete fidelity improvements.
• Ability to independently execute complex experimental efforts from concept through validated result.
• Strong Python skills in a scientific context and ability to build tools used by others.
• Experimental determination and judgment to balance investigation depth with iteration speed.
• Excellent communication skills and a team-first approach in a collaborative environment.

Nice to have

• Experience with quantum simulation frameworks such as QuTiP for gate and noise modeling.
• Experience deploying calibration or benchmarking procedures across large multi-qubit processors in an industrial or startup setting.
• Familiarity with randomized benchmarking variants, gate set tomography, cycle benchmarking, or other scalable error diagnostics.
• Publications or demonstrated results in high-fidelity entangling gates, error suppression, or quantum control.
• Experience mentoring junior scientists or leading small technical teams.

Culture & Benefits

• Substantial autonomy and ownership over gate-performance research and priorities.
• Collaboration across device design, fabrication, control systems, software, theory, and R&D.
• Full-time hybrid work arrangement.